SAA4700 Просмотр технического описания (PDF) - Philips Electronics

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SAA4700

VPS dataline processor

Philips Electronics 

Philips Semiconductors

VPS dataline processor

Preliminary specification

SAA4700

FEATURES

• Adaptive sync slicer with buffered

composite sync output VCS

• Adaptive data slicer

• Data rate clock regenerator

• Field selection and line 16

decoding

• Startcode and biphase check

• Data valid output

• Storage of data line information in a

40 bit register bank

• I2C-bus transmission

GENERAL DESCRIPTION

The SAA4700 is a bipolar integrated

circuit designed for use in dataline

receivers and incorporates a dataline

slicer and decoder. The slicer extracts

the dataline signal from the video

signal and regenerates the data

clock. It also provides signals for the

decoder in order to decode the binary

data that is transmitted in line 16 of

every first field of the composite video

signal (video programming signal and

video recording programming by

Teletext, VPS and VPT systems).

The decoded information out of words

5 and 11 to 14 is accessed via the

built-in I2C-bus interface. This

information then can be used for

programming a video cassette

recorder in order to start and stop a

recording of a television program at

the correct aligned time, regardless of

a delay or extension in the

transmission time of the required

program.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

VP

supply voltage (pins 15 and

16)

IP

Vi CVBS

total supply current

CVBS input signal

sync-to-white

(peak-to-peak value)

Tamb

operating ambient

temperature

MIN. TYP. MAX. UNIT

4.5 5

5.5 V

−

18

23

mA

0.5 1

0

−

1.4 V

+70 °C

ORDERING AND PACKAGE INFORMATION

EXTENDED TYPE

NUMBER

SAA4700

PINS

18

PACKAGE

PIN POSITION MATERIAL CODE

DIL

plastic SOT102 (1)

Note

1. SOT102-1; 1996 December 4.

March 1991

2

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