SAA4700 Просмотр технического описания (PDF) - Philips Electronics

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SAA4700

VPS dataline processor

Philips Electronics 

Philips Semiconductors

VPS dataline processor

Preliminary specification

SAA4700

PINNING

SYMBOL PIN DESCRIPTION

CVBS

1 video signal input (CVBS from TV)

SYNC

2 sync amplitude input (CVBS from TV)

GND1

3 analog ground (0 V)

GND2

4 digital ground (0 V)

Cblack

CSO

5 capacitor for black level

6 composite sync output

AD

SCL

SDA

7 address set input

8 I2C-bus clock line

9 I2C-bus data line

RS

10 reset input active LOW

TP

11 test point for line 16 decoder

DAV

12 data available output active LOW

Rosc

13

oscillator resistor for frequency

adjustment

CP

14 test point clock pulse

VP1

15 +5 V supply voltage (digital part)

VP2

16 +5 V supply voltage (analog part)

Cph

17 capacitor of phase detector

n.c.

18 not connected

PIN CONFIGURATION

handbook, halfpage

CVBS 1

18 n.c.

SYNC 2

17 Cph

GND1 3

GND2 4

16 VP2

15 VP1

Cblack 5 SAA4700 14 CP

CSO 6

13 Rosc

AD 7

12 DAV

SCL 8

11 TP

SDA 9

10 RS

MBH796

Fig.2 Pin configuration

External reset

The circuit provides an internal

power-on reset. When using this

facility pin 10 should be connected to

VP or, if external reset

(RESET = LOW) is to be used pin 10

should be prepared by connecting pin

10 via a 10 kΩ pull-up resistor to VP.

Reset forces the following:

- I2C-bus not to acknowledge

- DAV output to go HIGH (pin 12)

- I2C-bus transfer register to “FFF”

CVBS input

The CVBS signal is applied to the

sync separator (pin 2) via a

decoupling capacitor and to the data

slicer (pin 1) via an RC high-pass

filter.

To enable proper storage of the sync

value in the decoupling capacitor, the

sync generator output resistance

should not exceed 1 kΩ.

Black level

The capacitor connected to pin 5

stores the black level value for the

adaptive sync slicer.

Composite sync output (CSO)

A composite sync output signal for

customer application is provided

(pin 6).

DAV output

The data available output pin 12 is set

LOW after an error free dataline 16 is

received. DAV returnes to HIGH after

the beginning of the next first field. If

no valid data is available DAV

remains HIGH. A short duration pulse

of 1 µs (Fig.5) is inserted at the

beginning of dataline 16; it will ensure

that a HIGH-to-LOW transmission

occurs which can then be used for

triggering.

5 MHz VCO and phase detector

The resistor connected between pin

13 and VP2 determines the current

into the voltage controlled oscillator.

The RC network connected to pin 17

acts as a low-pass filter for the phase

detector.

Power supply

To prevent crosscoupling the circuit is

provided with separate ground and

supply pins for analog and digital

parts (pins 3, 4, 15 and 16).

March 1991

4

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