ISP1582 Просмотр технического описания (PDF) - Philips Electronics

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ISP1582

Hi-Speed Universal Serial Bus peripheral controller

Philips Electronics 

Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

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Fig 7. Oscilloscope reading: no resistor

and capacitor in the network.

Fig 8. Oscilloscope reading: with

resistor and capacitor in the

network.

8.13 Power-on reset

The ISP1582 requires a minimum pulse width of 500 µs.

Pin RESET_N can be either connected to VCC (using the internal POR circuit) or

externally controlled (by the microcontroller, ASIC, and so on). When VCC is directly

connected to pin RESET_N, the internal pulse width tPORP will be typically 200 ns.

The power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5

on the VCC(POR) curve (Figure 9).

t0 — The internal POR starts with a HIGH level.

t1 — The detector will see the passing of the trip level and a delay element will add

another tPORP before it drops to LOW.

t2-t3 — The internal POR pulse will be generated whenever VCC(POR) drops below

Vtrip for more than 11 µs.

t4-t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and

will remain LOW.

9397 750 13699

Preliminary data

VBAT(POR)

Vtrip

t0

t1

t2

t3

t4 t5

t

PORP

t

PORP

PORP(1)

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(1) PORP = power-on reset pulse.

Fig 9. POR timing.

Figure 10 shows the availability of the clock with respect to the external POR.

Rev. 03 — 25 August 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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