ISP1582 Просмотр технического описания (PDF) - Philips Electronics
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ISP1582 Datasheet PDF : 66 Pages
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Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Table 3:
VCC
ISP1582 pin status[1]
VCC(I/O)
State
0V
VCC
0V
VCC
0 V −> 3.3 V VCC
3.3 V
VCC
3.3 V
VCC
dead[2]
plug-out[3]
plug-in[4]
reset
normal
Pin
RESET_N
X
X
X
LOW
HIGH
INT_N
X
LOW
LOW
HIGH
HIGH
[1] X: Don’t care.
[2] Dead: The USB cable is plugged-out and VCC(I/O) is not available.
[3] Plug-out: The USB cable is not present but VCC(I/O) is available.
[4] Plug-in: The USB cable is being plugged-in and VCC(I/O) is available.
SUSPEND
X
HIGH
HIGH
LOW
LOW
DREQ
X
high-Z
high-Z
high-Z
high-Z
DATA[15:0]
X
input
high-Z
high-Z
high-Z
8.11 Interrupt
8.11.1 Interrupt output pin
The Interrupt Configuration register of the ISP1582 controls the behavior of the INT
output pin. The polarity and signaling mode of pin INT can be programmed by setting
bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see
Table 24. Bit GLINTENA of the Mode register (R/W: OCh) is used to enable pin INT.
Default settings after reset are active LOW and level mode. When pulse mode is
selected, a pulse of 60 ns is generated when the OR-ed combination of all interrupt
bits changes from logic 0 to logic 1.
Figure 4 shows the relationship between the interrupt events and pin INT.
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in
the Interrupt Enable register and the DMA Interrupt Enable register determine
whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register;
see Table 21.
Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation
of the INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt
Configuration register controls the generation of the INT signals for the IN pipe. Field
DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of
the INT signals for the OUT pipe; see Table 25.
9397 750 13699
Preliminary data
Rev. 03 — 25 August 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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