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IDT82P2288BB

Octal T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2288

OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

Type Pin No.

Description

TSCK[1] / MTSCK Output / Input L3 TSCK[1:8]: Transmit Side System Clock for Link 1 ~ 8

TSCK[2]

L1 In Transmit Clock Master mode, TSCKn outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1 mode)

TSCK[3]

K3 clock used to sample the signal on the corresponding TSDn and TSIGn pins and update the signal on the corre-

TSCK[4]

K1 sponding TSFSn pin.

TSCK[5]

J3 In Transmit Clock Slave mode, TSCKn inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz clock

TSCK[6]

J1 used to sample the signal on the corresponding TSDn, TSIGn and TSFSn pins. Selected by the TSLVCK bit (b1, T1/

TSCK[7]

H2 J1-010H / b1, E1-010H), the TSCK[1] can be used for all eight links.

TSCK[8]

H4

MTSCK: Multiplexed Transmit Side System Clock for Link 1 ~ 8

In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on the

corresponding MTSDA/MTSDB, MTSIGA/MTSIGB and MTSFS pins.

OSCI

Input

OSCO

CLK_SEL[0]

CLK_SEL[1]

CLK_SEL[2]

Output

Input

CLK_GEN_1.544 Output

CLK_GEN_2.048 Output

REFA_OUT

Output

REFB_OUT

Output

RESET

Input

TSCK[1:8]/MTSCK are Schmitt-triggered inputs/outputs with pull-up resistors.

Clock Generator

B13 OSCI: Crystal Oscillator Input

This pin is connected to an external clock source.

The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle

should be from 40% to 60%.

C13 OSCO: Crystal Oscillator Output

This pin outputs the inverted, buffered clock input from OSCI.

D15 CLK_SEL[2:0]: Clock Selection

C14 These three pins select the input clock signal:

B15 When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;

when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.

When the CLK_SEL[1:0] pins are ‘00’, the N is 1;

when the CLK_SEL[1:0] pins are ‘01’, the N is 2;

when the CLK_SEL[1:0] pins are ‘10’, the N is 3;

when the CLK_SEL[1:0] pins are ‘11’, the N is 4.

CLK_SEL[2:0] are Schmitt-trigger inputs.

A16 CLK_GEN_1.544: Clock Generator 1.544 MHz Output

This pin outputs the 1.544 MHz clock signal generated by the Clock Generator.

D14 CLK_GEN_2.048: Clock Generator 2.048 MHz Output

This pin outputs the 2.048 MHz clock signal generated by the Clock Generator.

A15 REFA_OUT: Reference Clock Output A

When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of

one of the eight links. The link is selected by the RO1[2:0] bits (b2~0, T1/J1-007H / b2~0, E1-007H).

When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH,... /

b0, E1-03EH,...). *

B14 REFB_OUT: Reference Clock Output B

When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of

one of the eight links. The link is selected by the RO2[2:0] bits (b5~3, T1/J1-007H / b5~3, E1-007H).

When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH,... /

b0, E1-03EH,...). *

Control Interface

A14 RESET: Reset (Active Low)

A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.

The RESET pin is a Schmitt-trigger input with a weak pull-up resistor.

Note:

* This feature is available in ZB revistion only.

Pin Description

7

March 22, 2004

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