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IDT82P2288BB

Octal T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2288

OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

Type Pin No.

Description

TSD[1] / MTSDA[1] Input

TSD[2] / MTSDB[1]

TSD[3]

TSD[4]

TSD[5] / MTSDA[2]

TSD[6] / MTSDB[2]

TSD[7]

TSD[8]

G2 TSD[1:8]: Transmit Side System Data for Link 1 ~ 8

G4 The data stream from the system side is input on these pins.

F2 In Transmit Clock Master mode, the TSDn pins are sampled on the active edge of the corresponding TSCKn.

F4 In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSDn pins are sam-

E2 pled on the active edge of the corresponding TSCKn or all eight TSDn pins are sampled on the active edge of

E4 TSCK[1].

D2

C2 MTSDA[1:2] / MTSDB[1:2]: Multiplexed Transmit Side System Data A / B for Link 1 ~ 8

In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSDA[1:2] pins or

the MTSDB[1:2] pins are used to input the data stream. Using a byte-interleaved multiplexing scheme, the

MTSDA[1]/MTSDB[1] pins input the data for Link 1 to Link 4, while the MTSDA[2]/MTSDB[2] pins input the data for

Link 5 to Link 8. The data on the MTSDA[1:2]/MTSDB[1:2] pins are sampled on the active edge of MTSCK.

TSIG[1] / MTSIGA[1] Input

TSIG[2] / MTSIGB[1]

TSIG[3]

TSIG[4]

TSIG[5] / MTSIGA[2]

TSIG[6] / MTSIGB[2]

TSIG[7]

TSIG[8]

TSD[1:8]/MTSDA[1:2]/MTSDB[1:2] are Schmitt-triggered inputs.

G3 TSIG[1:8]: Transmit Side System Signaling for Link 1 ~ 8

F1 The signaling bits are input on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/timeslot-

F3 aligned with the data input on the corresponding TSDn pin.

E1 In Transmit Clock Master mode, TSIGn is sampled on the active edge of the corresponding TSCKn.

E3 In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), TSIGn is sampled on

D1 the active edge of the corresponding TSCKn or all eight TSIGn are updated on the active edge of TSCK[1].

C1

B1 MTSIGA[1:2] / MTSIGB[1:2]: Multiplexed Transmit Side System Signaling A / B for Link 1 ~ 8

In Transmit Multiplexed mode, selected by the MTSDA bit (b2, T1/J1-010H / b2, E1-010H), the MTSIGA[1:2] pins or

the MTSIGB[1:2] pins are used to input the signaling bits. The signaling bits are located in the lower nibble (b5 ~ b8)

and are channel/timeslot-aligned with the data input on the corresponding MTSDA[1:2]/MTSDB[1:2] pins. Using the

byte-interleaved multiplexing scheme, the MTSIGA[1]/MTSIGB[1] pins input the signaling bits for Link 1 to Link 4,

while the MTSIGA[2]/MTSIGB[2] pins input the signaling bits for Link 5 to Link 8. The signaling bits on the

MTSIGA[1:2]/MTSIGB[1:2] pins are sampled on the active edge of MTSCK.

TSIG[1:8]/MTSIGA[1:2]/MTSIGB[1:2] are Schmitt-triggered inputs.

TSFS[1] / MTSFS Output / Input L2 TSFS[1:8]: Transmit Side System Frame Pulse for Link 1 ~ 8

TSFS[2]

K4 In T1/J1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate each F-bit or the first F-bit of every SF/

TSFS[3]

K2 ESF/T1 DM/SLC-96 multi-frame.

TSFS[4]

J4 In T1/J1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/

TSFS[5]

J2 T1 DM/SLC-96 multi-frame.

TSFS[6]

H1 In E1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame and/or

TSFS[7]

H3 Signaling Multi-frame.

TSFS[8]

G1 In E1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Sig-

naling Multi-frame.

TSFSn is updated/sampled on the active edge of the corresponding TSCKn. The active polarity of TSFSn is

selected by the FSINV bit (b1, T1/J1-042H,... / b1, E1-042H,...).

MTSFS: Multiplexed Transmit Side System Frame Pulse for Link 1 ~ 8

In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every SF/

ESF/T1 DM/SLC-96 multi-frame of one link on the multiplexed data bus.

In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame and/or

Signaling Multi-frame of one link on the multiplexed data bus.

MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit (b1, T1/

J1-042H,... / b1, E1-042H,...).

TSFS[1:8]/MTSFS are Schmitt-triggered inputs/outputs with pull-up resistors.

Pin Description

6

March 22, 2004

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