IDT82P2288BB Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

производитель

IDT82P2288BB

Octal T1/E1/J1 Long Haul / Short Haul Transceiver

Integrated Device Technology 

IDT82P2288

OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER

Name

Type Pin No.

Description

RSIG[1] / MRSIGA[1]

RSIG[2] / MRSIGB[1]

RSIG[3]

RSIG[4]

RSIG[5] / MRSIGA[2]

RSIG[6] / MRSIGB[2]

RSIG[7]

RSIG[8]

High-Z

Output

T2 RSIG[1:8]: Receive Side System Signaling for Link 1 ~ 8

T1 The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are chan-

P2 nel/timeslot-aligned with the data output on the corresponding RSDn pin.

N3 In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.

N1 In Receive Clock Slave mode, determined by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins are

M3 updated on the active edge of the corresponding RSCKn or all eight RSIGn are updated on the active edge of

M1 RSCK[1].

L4

MRSIGA[1:2] / MRSIGB[1:2]: Multiplexed Receive Side System Signaling A / B for Link 1 ~ 8

In Receive Multiplexed mode, the MRSIGA[1:2] pins or the MRSIGB[1:2] pins are used to output the extracted sig-

naling bits. The signaling bits are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data

output on the corresponding MRSDA[1:2]/MRSDB[1:2] pins. Using the byte-interleaved multiplexing scheme, the

MRSIGA[1]/MRSIGB[1] pins output the signaling bits from Link 1 to Link 4, while the MRSDA[2]/MRSDB[2] pins out-

put the signaling bits from Link 5 to Link 8. The signaling bits on the MRSIGA[1:2]/MRSIGB[1:2] pins are updated on

the active edge of the MRSCK. The signaling bits on MRSIGA[1:2] is the same as the signaling bits on

MRSIGB[1:2]. MRSIGB[1:2] are for back-up purpose.

RSFS[1] / MRSFS Output / Input R6 RSFS[1:8]: Receive Side System Frame Pulse for Link 1 ~ 8

RSFS[2]

N6 In T1/J1 Receive Clock Master mode, RSFSn outputs the pulse to indicate each F-bit, every second F-bit in SF

RSFS[3]

T5 frame, the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame or the first F-bit of every second SF multi-frame.

RSFS[4]

P5 In T1/J1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the

RSFS[5]

M5 start of a frame.

RSFS[6]

R4 In E1 Receive Clock Master mode, RSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame, Signal-

RSFS[7]

N4 ing Multi-frame, or both the CRC Multi-frame and Signaling Multi-frame, or the TS1 and TS16 overhead.

RSFS[8]

R3 In E1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the start

of a frame.

RSFSn is updated/sampled on the active edge of the corresponding RSCKn. The active polarity of RSFSn is deter-

mined by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).

MRSFS: Multiplexed Receive Side System Frame Pulse for Link 1 ~ 8

In Receive Multiplexed mode, MRSFS inputs the pulse at a rate of integer multiple of 125 µs to indicate the start of

a frame on the multiplexed data bus. MRSFS is sampled on the active edge of MRSCK. The active polarity of

MRSFS is determined by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).

RSFS[1:8]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.

RSCK[1] / MRSCK Output / Input T6 RSCK[1:8]: Receive Side System Clock for Link 1 ~ 8

RSCK[2]

P6 In Receive Clock Master mode, the RSCKn pins output a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1

RSCK[3]

M6 mode) clock used to update the signal on the corresponding RSDn, RSIGn and RSFSn pins.

RSCK[4]

R5 In Receive Clock Slave mode, the RSCKn pins input a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz

RSCK[5]

N5 clock used to update the signals on the corresponding RSDn and RSIGn pins and sample the signals on the corre-

RSCK[6]

T4 sponding RSFSn pins. Selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSCK[1] pin can be used

RSCK[7]

P4 for all eight links.

RSCK[8]

T3

MRSCK: Multiplexed Receive Side System Clock for Link 1 ~ 8

In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on the

corresponding MRSDA/MRSDB and MRSIGA/MRSIGB pins and sample the signal on the corresponding MRSFS

pin.

RSCK[1:8]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.

Pin Description

5

March 22, 2004

Share Link: