IDT72V36102 Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
производитель
IDT72V36102 Datasheet PDF : 29 Pages
| |||
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
highest numbered input is used as the most significant bit of the binary number
in each case. Valid programming values for the registers ranges from 1 to 16,380
for the IDT72V3682; 1 to 32,764 for the IDT72V3692; and 1 to 65,532 for the
IDT72V36102. After all the offset registers are programmed from port A, the port
B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal
operation. See Figure 3 for relevant offset register parallel programming timing
diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by port A Chip Select
(CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-
impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on port A are independent of any concurrent port B operation. Write and
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
The port B control signals are identical to those of port A with the exception
that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read
select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the
port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB is
COMMERCIAL TEMPERATURE RANGE
LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW,
and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and EFB/ORB is HIGH (see Table 3) . FIFO reads and writes
on port B are independent of any concurrent port A operation. Write and Read
cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setup and hold time constraints to the port Clocks for the port Chip Selects
and Write/Read selects are only for enabling write and read operations and are
not related to high-impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port’s Chip Select and Write/Read select may change
states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
H
X
X
X
X
High-Impedance
L
H
L
X
X
Input
L
H
H
L
↑
Input
L
H
H
H
↑
Input
L
L
L
L
X
Output
L
L
H
L
↑
Output
L
L
L
H
X
Output
L
L
H
H
↑
Output
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
H
X
X
X
X
High-Impedance
L
L
L
X
X
Input
L
L
H
L
↑
Input
L
L
H
H
↑
Input
L
H
L
L
X
Output
L
H
H
L
↑
Output
L
H
L
H
X
Output
L
H
H
H
↑
Output
11
Port Function
None
None
FIFO1 write
Mail1 write
None
FIFO2 read
None
Mail2 read (set MBF2 HIGH)
Port Function
None
None
FIFO2 write
Mail2 write
None
FIFO1 read
None
Mail1 read (set MBF1 HIGH)
Share Link: 