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IDT72V36102

3.3 VOLT CMOS SyncBiFIFO

Integrated Device Technology 

IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM

16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2

CLKA

CSA

LOW

tCLK

tCLKH tCLKL

COMMERCIAL TEMPERATURE RANGE

WRA

MBA

ENA

HIGH tENS2

tENS2

tENH

tENH

FFA

A0-A35

CLKB

HIGH tDS

tDH

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

EFB FIFO1 Empty

CSB LOW

2

tPOR

tPOR

W/RB

MBB

HIGH

LOW

ENB

tENS2

tENH

tA

B0-B35

W1

4679 drw 12

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

Figure 9. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)

18

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