HT47R20A-1 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT47R20A-1

R-F Type 8-Bit MCU

Holtek Semiconductor 

HT47R20A-1/HT47C20-1

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EEI

ETBI

ERTI

EIF

TBF

RTF

¾

Function

Control the master (global) interrupt (1= enabled; 0= disabled)

Control the external interrupt (1= enabled; 0= disabled)

Control the time base interrupt (1= enabled; 0= disabled)

Control the real time clock interrupt (1= enabled; 0= disabled)

External interrupt request flag (1= active; 0= inactive)

Time base request flag (1= active; 0= inactive)

Real time clock request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC0 (0BH) Register

Bit No.

0

1~3

4

5~7

Label

ETI

¾

TF

¾

Function

Control the timer/event counter interrupt (1= enabled; 0=disabled)

Unused bit, read as ²0²

Internal timer/event counter request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC1 (1EH) Register

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting.

Other interrupt requests may happen during this inter-

val, but only the interrupt request flag is recorded. If a

certain interrupt needs servicing within the service rou-

tine, the EMI bit and the corresponding bit of INTC0 or

INTC1 may be set allow interrupt nesting. If the stack is

full, the interrupt request will not be acknowledged,

even if the related interrupt is enabled, until the SP is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

All these kinds of interrupt have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack and then by

branching to subroutines at specified location(s) in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register and status

register (STATUS) is altered by the interrupt service

program which corrupts the desired control sequence,

the contents must be saved first.

External interrupt is triggered by a high to low transition

of INT and the related interrupt request flag (EIF; bit 4 of

INTC0) will be set. When the interrupt is enabled, and

the stack is not full and the external interrupt is active, a

subroutine call to location 04H will occur. The interrupt

request flag (EIF) and EMI bits will be cleared to disable

other interrupts.

The internal timer/event counter interrupt is initialized

by setting the timer/event counter interrupt request flag

(TF; bit 4 of INTC1), caused by a timer A or timer B over-

flow. When the interrupt is enabled, and the stack is not

full and the TF bit is set, a subroutine call to location 10H

will occur. The related interrupt request flag (TF) will be

reset and the EMI bit cleared to disable further inter-

rupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF; bit 5 of INTC0), caused

by a regular time base signal. When the interrupt is en-

abled, and the stack is not full and the TBF bit is set, a

subroutine call to location 08H will occur. The related in-

terrupt request flag (TBF) will be reset and the EMI bit

cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 6 of

INTC0), caused by a regular real time clock signal.

When the interrupt is enabled, and the stack is not full

and the RTF bit is set, a subroutine call to location 0CH

will occur. The related interrupt request flag (RTF) will be

reset and the EMI bit cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI instruc-

tion is executed or the EMI bit and the related interrupt

control bit are set to 1 (if the stack is not full). To return

from the interrupt subroutine, RET or RETI instruction

may be invoked. RETI will set the EMI bit to enable an in-

terrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Rev. 1.80

11

June 23, 2008

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