HT47R20A-1 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT47R20A-1

R-F Type 8-Bit MCU

Holtek Semiconductor 

HT47R20A-1/HT47C20-1

Timer/Event Counter

One 16-bit timer/event counter with PFD output or two

channels of RC type A/D converter is implemented in

the HT47R20A-1/HT47C20-1. The ADC/TM bit (bit 1 of

ADCR register) decides whether timer A and timer B is

composed of one 16-bit timer/event counter or timer A

and timer B composed of two channels RC type A/D

converter.

The TMRAL, TMRAH, TMRBL, TMRBH compose one

16-bit timer/event counter, when ADC/TM bit is ²0². The

TMRBL and TMRBH are timer/event counter preload

registers for lower-order byte and higher-order byte re-

spectively.

Using the internal clock, there are three reference time

base. The timer/event counter internal clock source may

come from the system clock or system clock/4 or RTC

time-out signal to generator an accurate time base.

Using external clock input allows the user to count exter-

nal events, count external RC type A/D clock, measure

time intervals or pulse widths, or generate an accurate

time base.

There are six registers related to the timer/event counter

operating mode. TMRAH ([20H]), TMRAL ([21H]),

TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and

ADCR ([25H]). Writing TMRBL only writes the data into

a low byte buffer, and writing TMRBH will write the data

and the contents of the low byte buffer into the

time/event counter preload register (16-bit) simulta-

neously. The timer/event counter preload register is

changed by writing TMRBH operations and writing

TMRBL will keep the timer/event counter preload regis-

ter unchanged.

Reading TMRAH will also latch the TMRAL into the low

byte buffer to avoid the false timing problem. Reading

TMRAL returns the contents of the low byte buffer. In

other words, the low byte of the timer/event counter can

not be read directly. It must read the TMRAH first to

make the low byte contents of the timer/event counter

be latched into the buffer.

If the timer/event counter is on, the TMRAH, TMRAL,

TMRBH and TMRBL cannot be read or written. To

avoid conflicting between timer A and timer B, the

TMRAH, TMRAL, TMRBH and TMRBL registers

should be accessed with ²MOV² instruction under

timer off condition.

The TMRC is the timer/event counter control register,

which defines the timer/event counter options.

The timer/event counter control register defines the op-

erating mode, counting enable or disable and active

edge.

Writing to timer B makes the starting value be placed in

the timer/event counter preload register, while reading

timer A yields the contents of the timer/event counter.

Timer B is timer/event counter preload register.

S y s te m C lo c k

S y s te m C lo c k /4

A /D C lo c k

R TC O ut

M

U

TM R 0

X

TE

D a ta B u s

O v e r flo w

1 6 - b it T im e r A

TQ

PFD

R

TM 2

P u ls e W id th

TM 1

M e a s u re m e n t T M 2

TM 0

M o d e C o n tro l T M 1

TO N

TM 0

1 6 - b it T im e r B

R e lo a d

P A 3 D a ta C T R L

Timer/Event Counter

Bit No.

0~2

3

4

5

6

7

Label

¾

TE

TON

TM0

TM1

TM2

Function

Unused bit, read as ²0²

Defines the TMR active edge of timer/event counter

(0=active on low to high; 1=active on high to low)

Enable or disable timer counting (0=disable; 1=enable)

Defines the operating mode (TM2, TM1, TM0)

000=Timer mode (system clock)

001=Timer mode (system clock/4)

010=Timer mode (RTC output)

011=A/D clock mode (RC oscillation decided by ADCR register)

100=Event counter mode (external clock)

101=Pulse width measurement mode (system clock/4)

110=Unused

111=Unused

TMRC (22H) Register

Rev. 1.80

16

June 23, 2008

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