HT47R20A-1 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT47R20A-1

R-F Type 8-Bit MCU

Holtek Semiconductor 

HT47R20A-1/HT47C20-1

time-out periods. If the RTC time-out occurs, the related

interrupt request flag (RTF; bit 6 of INTC0) is set. But if

the interrupt is enabled, and the stack is not full, a subrou-

tine call to location 0CH occurs. The real time clock

time-out signal can also be applied to be a clock source of

timer/event counter, so as to get a longer time-out period.

RT2 RT1 RT0 Clock Divided Factor

0

0

0

28*

0

0

1

29*

0

1

0

210*

0

1

1

211*

1

0

0

212

1

0

1

213

1

1

0

214

1

1

1

215

Note: ²*² not recommended to be used

Power Down Operation - HALT

The HALT mode is initialized by the HALT instruction

and results in the following.

· The system oscillator will turn off but the WDT oscilla-

tor or RTC oscillator keeps running (if the WDT oscil-

lator or the real time clock is selected).

· The contents of the on-chip RAM and registers remain

unchanged.

· The WDT will be cleared and recounted again (if the

WDT clock comes from the WDT oscillator or the real

time clock oscillator).

· All I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

· LCD driver is still running by ROM code option (if the

WDT OSC or RTC OSC is selected).

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a overflow. An external reset causes a

device initialization and the WDT overflow performs a

²warm reset². Examining the TO and PDF flags, the rea-

son for chip reset can be determined. The PDF flag is

cleared when the system power-up or executing the

CLR WDT instruction and is set when the HALT instruc-

tion is executed. The TO flag is set if a WDT time-out oc-

curs, it causes a wake-up that only resets the program

counter and SP, the others maintain their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by ROM code option. Awakening from an I/O port

stimulus, the program will resume execution of the next

instruction. If awakening from an interrupt, two se-

quences may happen. If the related interrupt is disabled

or the interrupt is enabled but the stack is full, the pro-

gram will resume execution at the next instruction. If the

interrupt is enabled and the stack is not full, the regular

interrupt response takes place.

If an interrupt request flag is set to ²1² before entering

the HALT mode the wake-up function of the related in-

terrupt will be disabled.

Once a wake-up event occurs, it takes 1024 (system

clock period) to resume normal operation. In other

words, a dummy period will be inserted after the

wake-up. If the wake-up results from an interrupt ac-

knowledgment, the actual interrupt subroutine execu-

tion is delayed by one more cycle. If the wake-up results

in the next instruction execution, this will execute imme-

diately after a dummy period has finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

· There are three ways in which a reset may occur.

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a warm reset

that just resets the program counter and SP leaving the

other circuits in their original state. Some registers re-

main unchanged during any other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means ²unchanged².

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

Rev. 1.80

14

June 23, 2008

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