LC6514B Просмотр технического описания (PDF) - SANYO -> Panasonic

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производитель

LC6514B

Single-Chip 4-bit Microcontroller (Low-Threshold Input, On-Chip FLT Driver)

SANYO -> Panasonic 

LC6514B

Continued from preceding page.

Mnemonic

LI data

S

Load AC with

immediate data

Store AC to M

L

Load AC from M

XM data

Exchange AC with

M. then modify DPH

with immediate data

X

Exchange AC with M

XI

XD

RTBL

Exchange AC with

M. then increment

DPL

Exchange AC with

M. then decrement

DPL

Read table data from

program ROM

LDZ data

LHI data

IND

DED

TAL

Load DPH with Zero

and DPL with

immediate data

respectively

Load DPH with

immediate data

Increment DPL

Decrement DPL

Transfer AC to DPL

TLA

Transfer DPL to AC

XAH

XAt

XA0

XA1

XA2

XA3

XHa

XH0

XH1

XLa

XL0

XL1

SFB flag

RFB flag

Exchange AC with

DPH

Exchange AC with

working register At

Exchange DPH with

working register Ha

Exchange DPL with

working register La

Set flag bit

Reset flag bit

JMP addr Jamp in the current

bank

JPEA

Jamp in the current

page modified by E

and AC

CZP addr Call subroutine in

the zero page

CAL addr Call subroutine in

the zero bank

RT

RTI

BANK

Return from

subroutine

Return from

interrrupt routine

Change bank

Instuction code

D7D6D5D4 D3D2D1D0

1100

I3 I2 I1 I0

Bytes Cycles

Function

1

1 AC←I3 I2 I1 I0

0000

0010

1

1 M (DP)←AC

0010

0001

1

1 AC←[M (DP)]

1 0 1 0 0 M2 M1 M0 1

1010

0000

1

2 (AC)↔ [M (DP)]

DPH←(DPH) –V–

0 M2 M1 M0

2 (AC)↔ [M (DP)]

1111

1110

1

1111

1111

1

0110

0011

1

2 (AC)↔ [M (DP)]

DPL←(DPL) +1

2 (AC)↔ [M (DP)]

DPL←(DPL) –1

2 AC, E←ROM

(PCh, E, AC)

1000

I3 I2 I1 I0

1

1 DPH←0

DPL←I3 I2 I1 I0

Description

Immediate data I3 I2 I1 I0 is loaded in

the AC.

The AC contents are stored in the

M(DP).

The M(DP) contents are loaded in the

AC.

The AC contents and the M(DP) contents

are exchanged. Then, the DPH contents

are modified with the contents of (DPH)V

0M2M1M0.

The AC contents and the M(DP)

contents are exchanged.

Status

flag

affected

ZF

ZF

ZF

ZF

The AC contents and the M(DP) contents ZF

are exchanged. Then, the DPL contents

are incremented +1.

The AC contents and the M(DP) contents ZF

are exchanged. Then, the DPL contents

are decremented –1.

The contents of ROM addressed by the

PC whose low-order 8 bits are replaced

with the E and AC contents are loaded

in the AC and E.

The DPH and DPL are loaded with 0 and

immediate data I3 I2 I1 I0 respectively.

Remarks

*1

The ZF is set/reset

according to the

result of (DPH) –V–

0M2M1M0.

The ZF is set/reset

according to the

DPH contents at the

time of instruction

execution.

The ZF is set/reset

according to the

result of (DPL+1).

The ZF is set/reset

according to the

result of (DPL–1).

0100

I3 I2 I1 I0

1

1110

1110

1

1110

1111

1

1111

0111

1

1110

1001

1

0010

0011

1

t1 t0

1110

0000

1

1110

0100

1

1110

1000

1

1110

1100

1

a

1111

1000

1

1111

1100

1

a

1111

0000

1

1111

0100

1

0 1 0 1 B3B2B1B0 1

0 0 0 1 B3B2B1B0 1

0 1 1 0 1 P10P9P8 2

P7P6P5P4 P3P2P1P0

1111

1010

1

1 0 1 1 P3P2P1P0 1

1 0 1 0 1 P10P9P8 2

P7P6P5P4 P3P2P1P0

0110

0010

1

0010

0010

1

1111

1101

1

1 DPH←I3 I2 I1 I0

1 DPL←(DPL) +1

1 DPL←(DPL) –1

1 DPL←(AC)

1 AC←(DPL)

1 (AC)↔ (DPH)

1 (AC)↔ (A0)

1 (AC)↔ (A1)

1 (AC)↔ (A2)

1 (AC)↔ (A3)

1 (DPH)↔ (H0)

1 (DPH)↔ (H1)

1 (DPL)↔ (L0)

1 (DPL)↔ (L1)

1 Fn←1

1 Fn←0

The DPH is loaded with immediate data

I3 I2 I1 I0.

The DPL contents are incremented +1. ZF

The DPL contents are incremented –1. ZF

The AC contents are transferred to the

DPL.

The DPL contents are transferred to the ZF

AC.

The AC contents and the DPH contents

are exchanged.

The AC contents and the contents of

working register A0, A1, A2, or A3

specified by t1 t0 are exchanged.

The DPH contents and the contents of

working register H0 or H1 specified by a

are exchanged.

The DPL contents and the contents of

working register L0 or L1 specified by a

are exchanged.

A flag specified by B3B2B1B0 is set.

A flag specified by B3B2B1B0 is reset. ZF

2 PC←PC11(or PC11) A jump to an address spesified by the

P10P9P8P7P6 PC11 (or PC11) and immediate data P10

P5P4P3P2P1P0 to P0 occurs.

1 PC7 to 0←(E, AC) A jump to an address spesified by the

contents of the PC whose low-order 8bits

are replaced with the E and AC contents

occurs.

1 STACK←(PC) +1 A subroutine in page 0 of bank 0 is

PC11 to 6,

PC1 to 0←0

PC5 to 2←

P3P2P1P0

called.

2 STACK←(PC) +2 A subroutine in bank 0 is called.

PC11 to 0←

0P10P9P8

P7P6P4P3P2P1P0

1 PC←(STACK)

A return from a subroutine occurs.

The flags are

divided into 4

groups of F0 to F3,

F4 to F7, F8 to F11,

F12 to F15.

The ZF is set/reset

according to the 4

bits including a

single bit specified

by immediate data

B3B2B1B0.

If the BANK and

JMP instructions

are executed

consecutively,

PC11→ PC11

1 PC←(STACK)

A return from an interrupt servicing

CF ZF←CSF, ZSF routine occurs.

ZF CF

1 PC11←(PC11)

The bank is changed.

Effective only when

used immediately

before the JMP

instruction.

Continued on next page.

No.1802–15/17

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