LC6514B Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC6514B

Single-Chip 4-bit Microcontroller (Low-Threshold Input, On-Chip FLT Driver)

SANYO -> Panasonic 

LC6514B

APPENDIX LC6510 Series Instruction Set (by Function)

Symbols

AC :

ACt :

CF :

CTL :

DP :

E:

EXTF :

Fn :

Meaning

Accumulator

Accmulator bit t

Carry flag

Control register

Data pointer

E register

External interrupt request flag

Flag bit n

M:

Memory

M (DP) : Memory addressed by DP

P (DPL) : Input/output port addressed by DPL

PC :

Program counter

STACK : Stack register

TM :

Timer

TMF : Timer (internal) interrupt request flag

At, Ha, La : Working resister

ZF :

Zero flag

( ), [ ] : Contents

←:

Transfer and direction

+:

Addition

–:

Subtraction

:

AND

:

OR

:

Exclusive OR

CLA

CLC

STC

CMA

Mnemonic

Clear AC

Clear CF

Set CF

Complement AC

Instuction code

D7D6D5D4 D3D2D1D0

1100

0000

Bytes

1

Cycles

Function

1 AC←0

1110

0001

1

1 CF←0

1111

0001

1

1 CF←1

1110

1011

1

1 AC←(AC)

INC

Increment AC

0000

1110

1

DEC

Decrement AC

0000

1111

1

RAL

Rotate AC left

0000

0001

1

through CF

TAE

Transfer AC to E

0000

0011

1

XAE

Exchange AC with E 0 0 0 0

1101

1

INM

Increment M

0010

1110

1

DEM

Decrement M

0010

1111

1

SMB bit Set M data bit

RMB bit Reset M data bit

AD

Add M to AC

0 0 0 0 1 0 B1B0

1

0 0 1 0 1 0 B1B0

1

0110

0000

1

1 AC←(AC)+1

1 AC←(AC)–1

1 AC0←(CF), ACn+1←

(ACn), CF←(AC3)

1 E←(AC)

1 AC↔ (E)

1 M (DP)←[M (DP) ]+1

1 M (DP)←[M (DP) ]–1

1 M (DP, B1B0)←1

1 M (DP), B1B0)←0

1 AC←(AC)+[M (DP)]

ADC

DAA

DAS

EXL

Add M to AC with CF 0 0 1 0

0000

1

Decimal adjust AC in 1 1 1 0

0110

1

addition

Decimal adjust AC in 1 1 1 0

1010

1

subtraction

Exclusive or M to AC 1 1 1 1

0101

1

1 AC←(AC)+[M (DP)]+

(CF)

1 AC←(AC)+6

1 AC←(AC)+10

1 AC←(AC) V [M (DP)]

AND

And M to AC

1110

0111

1

1 AC←(AC) [M (DP)]

OR

Or M to AC

1110

0101

1

1 AC←(AC) V [M (DP)]

CM

Compare AC with M 1 1 1 1

1011

1

1 [M (DP)]+ (AC)+1

Description

The AC contents are cleared.

Status

flag

affected

ZF

Remarks

*1

The CF is reset.

CF

The CF is set

CF

The AC contents are complemented ZF

(zero bits become 1, one bits

become 0).

The AC contents are incremented + ZF CF

1.

The AC contents are decremented – ZF CF

1.

The AC contents are shifted left

ZF CF

though the CF.

The AC contents are transferred to

the E.

The AC contents and the E contents

are exchanged.

The M (DP) contents are

ZF CF

incremented +1.

The M (DP) contents are

ZF CF

decremented –1.

A single bit of the M (DP) specified

by B1, B0 is set.

A single bit of the M (DP) specified ZF

by B1, B0 is set.

The AC contents and the M (DP)

ZF CF

contents are binary-added and the

result is placed in the AC.

The AC, CF, M (DP) contents are ZF CF

binary-added and the result is placed

in the AC.

6 is added to the AC contents.

ZF

10 is added to the AC contents.

ZF

The AC contents and the M (DP)

ZF

contents are exelusive-ORed and

the result is placed in the AC.

The AC contents and the M (DP)

ZF

contents are ANDed and the result is

placed in the AC.

The AC contents and the M (DP)

contents are ORed and the result is

placed in the AC.

The AC contents and the M (DP)

contents are compared and the CF

and ZF are set/reset.

ZF

ZF CF

Comparison result CF ZF

[M(DP)] > (AC) 0 0

[M(DP)] = (AC) 1 1

[M(DP)] < (AC) 1 0

CI data

Compare AC with

immediate data

0010

1100

2

0100

I3 I2 I1 I0

CLI data Compare DPL with

0010

1100

2

immediate data

0101

I3 I2 I1 I0

2 I3 I2 I1 I0+ (AC)+1

2 (DPL)VI3 I2 I1 I0

The AC contents and immediate

data I3 I2 I1 I0 are compared and

the ZF and CF are set/reset.

Comparison result CF ZF

I3I2I1I0> (AC)

I3I2I1I0 = (AC)

I3I2I1I0< (AC)

00

11

10

ZF CF

The DPL contents and immediate ZF

data I3 I2 I1 I0 are compared.

Continued on next page.

No.1802–14/17

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