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LC6514B Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC6514B Datasheet PDF : 17 Pages
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LC6514B
1-4. Notes for circuit design
1 How to fix C3, R6, C2, R2
Fix closed loop A discharge time constants C3, R6 and HOLD pin charge time constants C2, R2 so that closed loop
A fully discharges before the HOLD input voltage gets lower than VIL at the time of instantaneous break and the RES
input voltage is sure to get lower than VIL (a reset occurs) when V+ rises after instantaneous break where the HOLD
input voltage gets lower than VIL.
2 How to fix C3, R7
Fix RES pin charge time constats C3, R7 so that when power is applied initially or the HOLD mode is released the CF
OSC oscillates normally and the RES input voltage exceeds VIH and the program starts running.
3 How to fix R4, R5
Fix Tr bias constants R4, R5 so that when V+ rises after instantaneous break the RES input voltage gets lower than
VIL (brought to L-level) befor the HOLD input voltage exceeds VIH (brought to H-level).
4 How to fix C2, R3
Fix HOLD pin charge time constants C2, R3 so that when the HOLD mode is released from the backup mode the
HOLD input voltage does not exceed VIH (not brought to H-level) until the RES input voltage gets lower than
VIL(brought to L-level).
Fix C3, R7 and C2, R3 so that the time interval from the moment the HOLD input voltage exceeds VIH until the RES
input voltage exceeds VIH is longer than the CF OSC stabilizing time.
5 When the load is heavy or the polling interval is long
Since C1 discharges largely, increase the capacity of C1 or separate B detection from V+ and use a power supply or
signal that rises faster than V+.
1-5. Notes for software design
When the HOLD request signal is detected, the HALT instruction is executed immediately. A concrete example is
shown below.
1 An interrupt is inhibited before polling the HOLD request pin (HOLD pin).
2 Polling of the HOLD pin and the HALT instruction are programmed consecutively.
[Concrete example]
RCTL
BPO
HALT
AAA :
3
AAA
; EXTEN, TMEN0 (External, timer interrupt intibit)
; Polling of the HOLD pin (If H-level, a branch occurs to AAA.)
; The HOLD mode is entered.
No.180212/17

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