DS2156 Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
DS2156 Datasheet PDF : 265 Pages
| |||
DS2156
3.2.2 Transmit Side
Signal Name:
UT-ADDR0 to UT-ADDR4
Signal Description: Transmit UTOPIA Address
Signal Type:
Input
This 5-bit wide bus is driven by the ATM layer to poll and select the appropriate UTOPIA port. UT-ADDR4 is the
MSB; UT-ADDR0 is the LSB.
Signal Name:
UT-ENB
Signal Description: Transmit UTOPIA Enable
Signal Type:
Input
Active-low enable signal asserted by ATM layer during cycles when UT-DATAx contains valid cell data.
Signal Name:
UT-SOC
Signal Description: Transmit UTOPIA Start of Cell
Signal Type:
Input
Active-high signal asserted by ATM layer when UT-DATAx contains the first valid byte of the cell.
Signal Name:
UT-DATA0 to UT-DATA7
Signal Description: Transmit UTOPIA Data Bus
Signal Type:
Input
Byte-wide true data driven from ATM layer to one of the selected ports. UT-DATA7 is the MSB; UT-DATA0 is
the LSB.
Signal Name:
UT-CLAV
Signal Description: Transmit UTOPIA Cell Available
Signal Type:
Output
This active-high UT-CLAV signal is asserted by the DS2156 if it has a cell space available to accommodate a
complete cell from the ATM layer to the polled port.
Signal Name:
UT-2CLAV
Signal Description: Transmit UTOPIA 2 Cells Available
Signal Type:
Output
This active-high signal is asserted by the DS2156 to indicate that the transmitter can accommodate two cells. UT-
2CLAV0 is driven in multiplexed bus with 1CLAV mode as well as direct status mode for port 0. The timing of
this signal follows as that of UT-CLAV. This bus is not tri-statable.
Signal Name:
UT-UTDO
Signal Description: UTOPIA Transmit Data Output
Signal Type:
Output
Access to the data prior to the transmit formatter. Updated on the rising edge of TCLK. This output is normally
connected to TDATA.
Signal Name:
UT-CLK
Signal Description: Receive UTOPIA Clock
Signal Type:
Input
Transmit UTOPIA bus clock.
27 of 265
Share Link: 