DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

3.6 JTAG Test Access Port Pins

Signal Name:

Signal Description:

Signal Type:

JTRST

IEEE 1149.1 Test Reset

Input

JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from

low to high. This action sets the device into the JTAG DEVICE ID mode. Normal device operation is restored by

pulling JTRST low. JTRST is pulled high internally by a 10kΩ resistor operation.

Signal Name:

JTMS

Signal Description:

IEEE 1149.1 Test Mode Select

Signal Type:

Input

This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined

IEEE 1149.1 states. This pin has a 10kΩ pullup resistor.

Signal Name:

JTCLK

Signal Description:

IEEE 1149.1 Test Clock Signal

Signal Type:

Input

This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.

Signal Name:

JTDI

Signal Description:

IEEE 1149.1 Test Data Input

Signal Type:

Input

Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kΩ pullup

resistor.

Signal Name:

JTDO

Signal Description:

IEEE 1149.1 Test Data Output

Signal Type:

Output

Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be

left unconnected.

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