DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

3.1.2 Receive Side

Signal Name:

RLINK

Signal Description: Receive Link Data

Signal Type:

Output

T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a

frame.

E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.

Signal Name:

RLCLK

Signal Description: Receive Link Clock

Signal Type:

Output

T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.

E1 Mode: A 4kHz to 20kHz clock.

Signal Name:

RCLK

Signal Description: Receive Clock

Signal Type:

Output

1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.

Signal Name:

RCHCLK

Signal Description: Receive Channel Clock

Signal Type:

Output

A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK

when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is

enabled. Useful for parallel-to-serial conversion of channel data.

Signal Name:

RCHBLK

Signal Description: Receive Channel Block

Signal Type:

Output

A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels.

Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the

receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in

applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.

Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and

for per-channel conditioning. See Section 17 for details.

Signal Name:

RSER

Signal Description: Receive Serial Data

Signal Type:

Output

Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled.

Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name:

RSYNC

Signal Description: Receive Sync

Signal Type:

Input/Output

An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe

(IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to

output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin

can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied.

Signal Name:

RFSYNC

Signal Description: Receive Frame Sync

Signal Type:

Output

An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.

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