DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

3.2 UTOPIA Bus

3.2.1 Receive Side

Signal Name:

UR-ADDR0 to UR-ADDR4

Signal Description: Receive UTOPIA Address

Signal Type:

Input

5-bit UTOPIA address bus driven from ATM layer to select the appropriate UTOPIA port. RX_UTOP_ADDR4 is

the MSB; RX_UTOP_ADDR0 is the LSB.

Signal Name:

UR-ENB

Signal Description: Receive UTOPIA Enable

Signal Type:

Input

Active-low signal asserted by the ATM layer to indicate that UR-DATAx and UR-SOC are sampled at the end of

the next cycle.

Signal Name:

UR-SOC

Signal Description: Receive UTOPIA Start of Cell

Signal Type:

Output

Active-high signal asserted by the DS2156 when UR-DATAx contains the first valid byte of a cell and is enabled

only in cycles following those with UR-ENB asserted and cell transfer is in progress.

Signal Name:

UR-DATA0 to UR-DATA7

Signal Description: Receive UTOPIA Data Bus

Signal Type:

Output

This byte-wide data bus is driven by the DS2156 in response to the selection of one of the UTOPIA ports by the

ATM layer for cell transfer. This bus is tri-statable and is enabled only in cycles following those with UR-ENB

asserted and cell transfer is in progress for a port. UR-DATA7 is the MSB; UR-DATA0 is the LSB.

Signal Name:

UR-CLAV

Signal Description: Receive UTOPIA Cell Available

Signal Type:

Output

The active-high UR-CLAV signal is asserted if a complete cell is available for transfer to the ATM layer for the

polled port. If UR-ADDRx does not match with any one of UTOPIA port addresses, this signal is tri-stated at the

chip level using the control lines detailed below. UR-CLAV0 is driven in multiplexed bus with 1CLAV polling

mode as well as direct status mode.

Signal Name:

UR-CLK

Signal Description: Receive UTOPIA Clock

Signal Type:

Input

Receive UTOPIA bus clock.

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