CY8C5246PVI-091 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY8C5246PVI-091

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®5: CY8C52 Family Data Sheet

3-72 MHz

IMO

4-33 MHz

ECO

Figure 6-1. Clocking Subsystem

External IO

or DSI

0-33 MHz

32 kHz ECO

1,33,100 kHz

ILO

12-72 MHz

Doubler

24-40 MHz

PLL

System

Clock Mux

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

7

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Bus/CPU Clock

Divider 16 bit

s

Analog Clock k

Divider 16 bit e

w

s

Analog Clock k

Divider 16 bit e

w

7

s

Analog Clock k

Divider 16 bit e

w

s

Analog Clock k

Divider 16 bit e

w

6.1.1 Internal Oscillators

6.1.1.1 Internal Main Oscillator

In most designs the IMO is the only clock source required, due

to its ±1% accuracy. The IMO operates with no external compo-

nents and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±1% at 3 MHz, up to ±10% at 72 MHz. The

IMO, in conjunction with the PLL, allows generation of up to a 66

MHz clock with ±1% accuracy.

The IMO provides clock outputs at 3, 6, 12, 24, 48, and 72 MHz.

6.1.1.2 Clock Doubler

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler works for input frequency ranges of 6 to

24 MHz (providing 12 to 72 MHz at the output). It can be

configured to use a clock from the IMO, MHzECO, or the DSI

(external pin).

6.1.1.3 Phase-Locked Loop

The PLL allows low frequency, high accuracy clocks to be multi-

plied to higher frequencies. This is a tradeoff between higher

clock frequency and accuracy and, higher power consumption

and increased startup time.

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 40 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The most common

PLL use is to multiply the IMO clock at 3 MHz, where it is most

accurate to generate the CPU and system clocks up to the

device’s maximum frequency.

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO, DSI (external pin), or doubler. The PLL clock source

can be used until lock is complete and signaled with a lock bit.

Disable the PLL before entering low power modes.

6.1.1.4 Internal Low Speed Oscillator

The ILO provides clock frequencies for low power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

The 1 kHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW).

The central timewheel is a 1 kHz, free running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic inter-

rupts for timing purposes or to wake the system from a low power

mode. Firmware can reset the central timewheel.

Document Number: 001-55034 Rev. *A

Page 20 of 85

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