CY8C5246PVI-091 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C5246PVI-091 Datasheet PDF : 85 Pages
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PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
Table 4-6. Interrupt Vector Table (continued)
Interrupt # Cortex-M3 Exception #
Fixed Function
7
23
PICU[3]
8
24
PICU[4]
9
25
PICU[5]
10
26
PICU[6]
11
27
PICU[12]
12
28
PICU[15]
13
29
Comparator Int
14
30
15
31
Reserved
I2C
16
32
CAN
17
33
Timer/Counter0
18
34
Timer/Counter1
19
35
Timer/Counter2
20
36
Timer/Counter3
21
37
USB SOF Int
22
38
USB Arb Int
23
39
USB Bus Int
24
40
USB Endpoint[0]
25
41
USB Endpoint Data
26
42
Reserved
27
43
Reserved
28
44
Reserved
29
45
Decimator Int
30
46
phub_err_int
31
47
eeprom_fault_int
5. Memory
5.1 Static RAM
CY8C52 Static RAM (SRAM) is used for temporary data storage.
Code can be executed at full speed from the portion of SRAM
that is located in the code space. This process is slower from
SRAM above 0x20000000. The device provides up to 64 KB of
SRAM. The CPU or the DMA controller can access all of SRAM.
The SRAM can be accessed simultaneously by the Cortex-M3
CPU and the DMA controller if accessing different 32 KB blocks.
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main Flash memory area contains up to
256 KB of user program space.
Up to an additional 32 KB of Flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC Flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected. The Flash output is 9 bytes wide with 8 bytes of data
and 1 byte of ECC data.
The CPU or DMA controller read both user code and bulk data
located in Flash through the cache controller. This provides
DMA
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
UDB
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
higher CPU performance. If ECC is enabled, the cache controller
also performs error checking and correction. Flash programming
is performed through a special interface and preempts code
execution out of Flash. Code execution out of cache may
continue during Flash programming as long as that code is
contained inside the cache.
The Flash programming interface performs Flash erasing,
programming and setting code protection levels. Flash In
System Serial Programming (ISSP), typically used for production
programming, is possible through both the SWD and JTAG inter-
faces. In-system programming, typically used for bootloaders, is
also possible using serial interfaces such as I2C, USB, UART,
and SPI, or any communications protocol.
5.3 Flash Security
All PSoC devices include a flexible Flash protection model that
prevents access and visibility to on-chip Flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or configu-
ration data.
The device offers the ability to assign one of four protection
levels to each row of Flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete Flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
Document Number: 001-55034 Rev. *A
Page 15 of 85
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