CY8C5246PVI-091 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C5246PVI-091 Datasheet PDF : 85 Pages
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PRELIMINARY
PSoC®5: CY8C52 Family Data Sheet
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32
interrupts from peripherals, as shown in Table 4-5.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Exception
Number
Exception Type
Priority
1
Reset
-3 (highest)
2
NMI
-2
3
Hard fault
-1
4
5
6
7 – 10
11
12
13
14
15
16 – 47
MemManage
Bus fault
Usage fault
-
SVC
Debug monitor
-
PendSV
SYSTICK
IRQ
Programmable
Programmable
Programmable
-
Programmable
Programmable
-
Programmable
Programmable
Programmable
Exception Table
Address Offset
Function
0x00
Starting value of R13 / MSP
0x04
Reset
0x08
Non maskable interrupt
0x0C
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
0x10
Memory management fault, for example, instruction
fetch from a nonexecutable region
0x14
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
0x18
Typically caused by invalid instructions or trying to
switch to ARM mode
0x1C – 0x28
Reserved
0x2C
System service call via SVC instruction
0x30
Debug monitor
0x34
Reserved
0x38
Deferred request for system service
0x3C
System tick timer
0x40 – 0x3FC
Peripheral interrupt request #0 - #31
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 41.
The Nested Vectored Interrupt Controller (NVIC) handles inter-
rupts from the peripherals, and passes the interrupt vectors to
the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:
32 interrupts. Multiple sources for each interrupt.
Configurable number of priority levels: from 3 to 8.
Dynamic reprioritization of interrupts.
Priority Grouping. This allows selection of preempting and non
preempting interrupt levels.
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Table 4-6. Interrupt Vector Table
Interrupt # Cortex-M3 Exception #
Fixed Function
DMA
0
16
Low voltage detect (LVD) phub_termout0[0]
1
17
2
18
3
19
Cache/ECC
Reserved
Sleep (Pwr Mgr)
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
4
20
5
21
PICU[0]
PICU[1]
phub_termout0[4]
phub_termout0[5]
6
22
PICU[2]
phub_termout0[6]
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
Document Number: 001-55034 Rev. *A
Page 14 of 85
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