CY8C5246PVI-091 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY8C5246PVI-091

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC®5: CY8C52 Family Data Sheet

Table 4-2. Cortex M3 CPU Registers (continued)

Register

BASEPRI

CONTROL

Description

A register of up to nine bits that define the

masking priority level. When set, it disables all

interrupts of the same or higher priority value. If

set to 0 then the masking function is disabled.

A 2-bit register for controlling the operating

mode.

Bit 0: 0 = privileged level in thread mode, 1 = user

level in thread mode.

Bit 1: 0 = default stack (MSP) is used, 1 =

alternate stack is used. If in thread mode or user

level then the alternate stack is the PSP. There

is no alternate stack for handler mode; the bit

must be 0 while in handler mode.

4.2 Cache Controller

The CY8C52 family adds an instruction cache between the CPU

and the Flash memory. This guarantees a faster instruction

execution rate. The Flash cache also reduces system power

consumption by requiring less frequent Flash access.

4.3 DMA and PHUB

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

„ A central hub that includes the DMA controller, arbiter, and

router

„ Multiple spokes that radiate outward from the hub to most

peripherals

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

4.3.1 PHUB Features

„ CPU and DMA controller are both bus masters to the PHUB

„ Eight Multi-layer AHB Bus parallel access paths (spokes) for

peripheral access

„ Simultaneous CPU and DMA access to peripherals located on

different spokes

„ Simultaneous DMA source and destination burst transactions

on different spokes

„ Supports 8, 16, 24, and 32-bit addressing and data

Table 4-3. PHUB Spokes and Peripherals

PHUB Spokes

Peripherals

0

SRAM

1

IOs, PICU, EMIF

2

PHUB local configuration, Power manager,

Clocks, IC, SWV, EEPROM, Flash

programming interface

3

Analog interface and trim, Decimator

4

USB, CAN, I2C, Timers, Counters, and PWMs

5

Reserved

6

UDBs group 1

7

UDBs group 2

4.3.2 DMA Features

„ 24 DMA channels

„ Each channel has one or more Transaction Descriptors (TDs)

to configure channel behavior. Up to 128 total TDs can be

defined

„ TDs can be dynamically updated

„ Eight levels of priority per channel

„ Any digitally routable signal, the CPU, or another DMA channel,

can trigger a transaction

„ Each channel can generate up to two interrupts per transfer

„ Transactions can be stalled or canceled

„ Supports transaction size of infinite or 1 to 64k bytes

„ Large transactions may be broken into smaller bursts of 1 to

127 bytes

„ TDs may be nested and/or chained for complex transactions

4.3.3 Priority Levels

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested simul-

taneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100% of the bus bandwidth. If a tie occurs

on two DMA requests of the same priority level, a simple round

robin method is used to evenly share the allocated bandwidth.

The round robin allocation can be disabled for each DMA

channel, allowing it to always be at the head of the line. Priority

levels 2 to 7 are guaranteed the minimum bus bandwidth shown

in Table 4-4 after the CPU and DMA priority levels 0 and 1 have

satisfied their requirements.

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

Document Number: 001-55034 Rev. *A

Page 12 of 85

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