UPD70741GC-25-8EU Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD70741GC-25-8EU

V821™ 32-/16-BIT MICROPROCESSOR

NEC => Renesas Technology 

µPD70741

3.3.2 System register set

System registers are used to control the state of the CPU and store interrupt information.

Table 3-2. System Register Numbers

No.

Register name

0

EIPC

1

EIPSW

2

FEPC

3

FEPSW

4

ECR

5

PSW

6

7

8-23

24

25

PIR

TKCW

Reserved

CHCW

ADTRE

26-31 Reserved

Use

Registers for saving the current

status upon the occurrence of an

exception or interrupt

Registers for saving the current

status upon the occurrence of an

NMI or double exception

Exception source register

Program status word

Processor ID register

Task control word

Explanation

Retain the contents of PC and PSW if an exception or

interrupt occurs. Note, however, that there is only one

pair of these registers.

When multiple interrupts are allowed, therefore, the

contents of the registers must be saved by the program.

Retain the contents of PC and PSW if an

NMI or double exception occurs.

Stores the source of an exception, maskable interrupt, or

NMI. The upper 16 bits of this register are called

"FECC" and set to the exception code of an NMI/double

exception. The lower 16 bits are called "EICC" and set

to the exception code of an exception/interrupt.

The program status word is a set of flags indicating the

state of the program (result of executing an instruction)

and the state of the CPU.

Used to identify a CPU type number.

Used to control a floating-point operation.

Cache control word

Address trap register

Used to control the built-in instruction cache.

Stores the address used to detect an address match with

PC, and to generate an address trap.

Read and write operations made to these system registers can be performed using the system register load/store

instructions (LDSR and STSR) with the system register numbers specified.

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