µPD70741
2.9 Watchdog Timer (WDT)
This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdog
timer overflows, the WDTOUT pin becomes active.
2.10 Clock Generator (CG)
Supplies clock pulses at a frequency five times greater than that of the oscillator connected to pins X1 and X2 (when
the built-in PLL is being used) or at half the frequency (when the built-in PLL is not being used) of the operating clock
pulses for the CPU. Also, instead of connecting an oscillator, external clock pulses can be input.
2.11 Bus Arbitration Unit (BAU)
Arbitrates any contention over bus mastership between the bus masters (CPU, DRAMC, DMAC, external bus
master). Bus mastership can be switched in each bus cycle and also in the idle state.
2.12 Port
Port 0 provides a total of ten input/output port pins. The pins can be used as either port or control pins.
13