ADT7467ARQZ-R71 Просмотр технического описания (PDF) - ON Semiconductor
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ADT7467ARQZ-R71 Datasheet PDF : 77 Pages
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SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7467 is carried out
using the serial system management bus (SMBus). The
ADT7467 is connected to this bus as a slave device under
the control of a master controller, which is usually (but not
necessarily) the ICH.
The ADT7467 has a fixed 7-bit serial bus address of 0101110 or
0x2E. The read/write bit must be added to get the 8-bit address
(01011100 or 0x5C). Data is sent over the serial bus in
sequences of nine clock pulses: eight bits of data followed by an
acknowledge bit from the slave device. Transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition might be interpreted as a stop signal when the clock
is high. The number of data bytes that can be transmitted over
the serial bus in a single read or write operation is only limited
by what the master and slave devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse. This is known as a no acknowledge. The
master then takes the data line low during the low period before
the 10th clock pulse, and then high during the 10th clock pulse
to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation. It is not possible to mix a read and a write
in one operation, however, because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the ADT7467, write operations contain either one or two
bytes, and read operations contain one byte. To write data to a
device data register or read data from it, the address pointer
register must first be set. The first byte of a write operation
always contains an address, which is stored in the address
pointer register, and the second byte, if there is a second byte, is
written to the register selected by the address pointer register.
ADT7467
This write operation is illustrated in Figure 16. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register, and the second data byte is the data
written to that internal data register.
When reading data from a register, there are two possibilities:
• If the address pointer register value of the ADT7467 is
unknown or not the desired value, it must be set to the
correct value before data can be read from the desired data
register. This is achieved by writing a data byte containing
the register address to the ADT7467. This is shown in
Figure 17. A read operation is then performed consisting of
the serial bus address and the R/W bit set to 1, followed by
the data byte read from the data register. This is shown in
Figure 18.
• If the address pointer register is known to be at the desired
address, data can be read from the corresponding data
register without first writing to the address pointer register,
as shown in Figure 18.
If the address pointer register is already at the correct value, it is
possible to read a data byte from the data register without first
writing to the address pointer register. However, it is not
possible to write data to a register without writing to the
address pointer register, because the first data byte of a write is
always written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7467 also supports the read byte protocol.
(See the Intel System Management Bus Specifications Rev. 2 for
more information.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
Rev. 3 | Page 11 of 77 | www.onsemi.com
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