ADSP-21366BBCZ-1AA Просмотр технического описания (PDF) - Analog Devices

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ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PIN FUNCTION DESCRIPTIONS

The processor’s pin definitions are listed below. Inputs identi-

fied as synchronous (S) must meet timing requirements with

respect to CLKIN (or with respect to TCK for TMS and TDI).

Inputs identified as asynchronous (A) can be asserted asynchro-

nously to CLKIN (or to TCK for TRST). Tie or pull unused

inputs to VDDEXT or GND, except for the following:

DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and

AD15–0. Note: These pins have pull-up resistors.

Table 6. Pin Descriptions

State During and

Pin

Type

After Reset

Function

AD15–0

I/O/T

(pu)

Three-state with

pull-up enabled

Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA

unit output addresses and data for peripherals on these multiplexed pins. The multiplex

state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit

mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin

operation, refer to the ADSP-2136x SHARC Processor Hardware Reference .

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16

external address bits, ADDR23–8; ALE is used in conjunction with an external latch to

retain the values of the ADDR23–8.

For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x

SHARC Processor Hardware Reference.

RD

O

Three-state, driven Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16-

(pu)

high1

bit data from an external memory device. When AD15–0 are flags, this pin remains

deasserted. RD has a 22.5 kΩ internal pull-up resistor.

WR

O

Three-state, driven Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or

(pu)

high1

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

ALE

O

Three-state, driven Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a

(pd)

low1

new address on the parallel port address pins. On reset, ALE is active high. However, it

can be reconfigured using software to be active low. When AD15–0 are flags, this pin

remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

FLAG[0]/IRQ0/SPI I/O

FLG[0]

FLAG[0] INPUT

FLAG0/Interrupt Request0/SPI0 Slave Select.

FLAG[1]/IRQ1/SPI I/O

FLG[1]

FLAG[1] INPUT

FLAG1/Interrupt Request1/SPI1 Slave Select.

FLAG[2]/IRQ2/SPI I/O

FLG[2]

FLAG[2] INPUT

FLAG2/Interrupt Request 2/SPI2 Slave Select.

FLAG[3]/TMREXP/ I/O

SPIFLG[3]

FLAG[3] INPUT

FLAG3/Timer Expired/SPI3 Slave Select.

DAI_P20–1

I/O/T

(pu)

Three-state with

programmable

pull-up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The

SRU configuration registers define the combination of on-chip peripheral inputs or

outputs connected to the pin and to the pin’s output enable. The configuration registers

of these peripherals then determine the exact behavior of the pin. Any input or output

signal present in the SRU can be routed to any of these pins. The SRU provides the

connection from the serial ports, input data port, precision clock generators and timers,

sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ

pull-up resistors that are enabled on reset. These pull-ups can be disabled using the

DAI_PIN_PULLUP register.

The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,

S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.

Rev. G | Page 11 of 56 | March 2011

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