ADSP-21366BBCZ-1AA Просмотр технического описания (PDF) - Analog Devices

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ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Reset

Table 12. Reset

Parameter

Min

Unit

Timing Requirements

tWRST1

tSRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4 × tCK

ns

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

Figure 9. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 13. Interrupts

Parameter

Timing Requirement

tIPW

IRQx Pulse Width

tSRST

Min

2 × tPCLK +2

Unit

ns

DAI_P20–1

FLAG2–0

(IRQ2–0)

tIPW

Figure 10. Interrupts

Rev. G | Page 19 of 56 | March 2011

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