ADSP-21366BBCZ-1AA Просмотр технического описания (PDF) - Analog Devices

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ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP pin).

Table 14. Core Timer

Parameter

Switching Characteristic

tWCTIM

TMREXP Pulse Width

Min

2 × tPCLK – 1

FLAG3

(TMREXP)

tWCTIM

Figure 11. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 15. Timer PWM_OUT Timing

Parameter

Switching Characteristic

tPWMO

Timer Pulse Width Output

Min

2 tPCLK – 1

DAI_P20–1

(TIMER2–0)

tPWMO

Figure 12. Timer PWM_OUT Timing

Max

2(231 – 1) tPCLK

Unit

ns

Unit

ns

Rev. G | Page 20 of 56 | March 2011

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