ADSP-21365(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21365
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 23. 16-Bit Memory Read Cycle

Parameter

Min

Timing Requirements

tDRS

AD15–0 Data Setup Before RD High

3.3

tDRH

AD15–0 Data Hold After RD High

0

Switching Characteristics

tALEW

tADAS1

ALE Pulse Width

AD15–0 Address Setup Before ALE Deasserted

2 × tPCLK – 2.0

tPCLK – 2.5

tALERW

tRRH2

ALE Deasserted to Read Asserted

Delay Between RD Rising Edge to Next Falling Edge

2 × tPCLK – 3.8

H + tPCLK – 1.4

tRWALE

Read Deasserted to ALE Asserted

F + H + 0.5

tRDDRV

tADAH1

tALEHZ1

ALE Address Drive After Read High

AD15–0 Address Hold After ALE Deasserted

ALE Deasserted to Address/Data15–0 in High Z

F + H + tPCLK – 2.3

tPCLK – 2.3

tPCLK

tRW

RD Pulse Width

D – 2.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK

H = tPCLK (if a hold cycle is specified, else H = 0)

F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)

tPCLK = (peripheral) clock period = 2 × tCCLK

1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

2 This parameter is only available when in EMPP = 0 mode.

Max

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

tPCLK + 3.0

ns

ns

ALE

RD

tALEW

tALERW

tRRH

tRW

tRWALE

WR

AD15-0

tADAS

tALEHZ

tADAH

VALID ADDRESS

tDRS

tDRH

VALID DATA

tR DDRV

VALID DATA

VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Figure 19. Read Cycle for 16-Bit Memory Timing

Rev. A | Page 28 of 52 | December 2006

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