ADSP-21365(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21365
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the ADSP-2136x

is accessing external memory space.

Table 22. 8-Bit Memory Read Cycle

Parameter

Min

Timing Requirements

tDRS1

AD7–0 Data Setup Before RD High

3.3

tDRH

AD7–0 Data Hold After RD High

0

tDAD1

AD15–8 Address to AD7–0 Data Valid

Switching Characteristics

tALEW

tADAS2

tRRH

ALE Pulse Width

AD15–0 Address Setup Before ALE Deasserted

Delay Between RD Rising Edge to Next

Falling Edge

2 × tPCLK – 2.0

tPCLK – 2.5

H + tPCLK – 1.4

tALERW

ALE Deasserted to Read Asserted

2 × tPCLK – 3.8

tRWALE

tADAH2

Read Deasserted to ALE Asserted

AD15–0 Address Hold After ALE Deasserted

F + H + 0.5

tPCLK – 2.3

tALEHZ2

ALE Deasserted to AD7–0 Address in High Z

tPCLK

tRW

RD Pulse Width

D – 2.0

tRDDRV

AD7–0 ALE Address Drive After Read High

F + H + tPCLK – 2.3

tADRH

AD15–8 Address Hold After RD High

H

tDAWH

AD15–8 Address to RD High

D + tPCLK – 4.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK

H = tPCLK (if a hold cycle is specified, else H = 0)

F = 7 × tPCLK (if FLASH_MODE is set, else F = 0)

tPCLK = (peripheral) clock period = 2 × tCCLK

1 The timing specified here is sufficient to satisfy either tDAD or tDRS as they are independent.

2 On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Max

D + tPCLK – 5.0

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

tPCLK + 3.0

ns

ns

ns

ns

ns

Rev. A | Page 26 of 52 | December 2006

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