ADSP-21365(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-21365 Datasheet PDF : 52 Pages
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, data channel A, data channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 26. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tHFSE1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tSDRE1
tHDRE1
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
12
ns
24
ns
Switching Characteristics
tDFSE2
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
tHOFSE2
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
tDDTE2
tHDTE2
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
9.5
ns
2
ns
9.5
ns
2
ns
Table 27. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tHFSI1
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
Min
Max
Unit
7
ns
2.5
ns
7
ns
2.5
ns
Switching Characteristics
tDFSI2
tHOFSI2
tDFSIR2
tHOFSIR2
tDDTI2
tHDTI2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
tSCLKIW
Transmit or Receive SCLK Width
1 Referenced to the sample edge.
2 Referenced to drive edge.
3
ns
–1.0
ns
8
ns
–1.0
ns
3
ns
–1.0
ns
0.5tSCLK – 2 0.5tSCLK + 2 ns
Rev. A | Page 31 of 52 | December 2006
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