ADSP-21365(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21365
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Reset

Table 14. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST1

RESET Pulse Width Low

4tCK

ns

tSRST

RESET Setup Before CLKIN Low

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

tSRST

Figure 10. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 15. Interrupts

Parameter

Timing Requirement

tIPW

IRQx Pulse Width

Min

2 × tPCLK + 2

Max

DAI20-1

FLAG2-0

(IRQ2-0)

tIPW

Figure 11. Interrupts

Unit

ns

Rev. A | Page 21 of 52 | December 2006

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