28F016SV FlashFile™ MEMORY
E
4.8 Device Configuration Code
R
R
R
R
R
RB2
RB1
RB0
7
6
5
4
DCC.2-DCC.0 = RY/BY# CONFIGURATION
(RB2–RB0)
001 = Level Mode (Default)
010 = Pulse-On-Program
011 = Pulse-On-Erase
100 = RY/BY# Disabled
101 = Pulse-On-Program/Erase
3
2
1
0
NOTES:
Undocumented combinations of RB2–RB0 are
reserved by Intel Corporation for future
implementations and should not be used.
DCC.7–DCC.3 =
RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code.
Set these bits to “0” when writing the desired RY/BY# configuration to the device.
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