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28F016SV Просмотр технического описания (PDF) - Intel

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28F016SV Datasheet PDF : 63 Pages
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E
28F016SV FlashFile™ MEMORY
4.5 Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
NOTES:
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase,
erase suspend, or data program) before the
appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS
1 = Error in Data Program
0 = Data Program Successful
If DWS and ES are set to “1” during an erase
attempt, an improper command sequence was
entered. Clear the CSR and attempt the
operation again.
CSR.3 = VPP STATUS
1 = VPP Error Detect, Operation Abort
0 = VPP OK
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level only after the Data
Program or Erase command sequences have
been entered, and informs the system if VPP has
not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPLK(max)
and VPPH1(min), between VPPH1(max) and
VPPH2(min) and above VPPH2(max).
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
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