HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor
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производитель
HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
0x22 62.6688 MHz 0x2c 81.1008 MHz
0x23 64.5120 MHz 0x2D 82.9440 MHz
0x24 66.3552 MHz Other values Reserved
IF BIT 6 is `0'
When the CPU writes to bits 5:0 of this register, these bits are stored in a temporary buffer, which is not
transferred to the PLL until the next time the PLL lock signal becomes inactive. This means that for a new
value to take effect, it is necessary for the device to enter DEEP SLEEP mode first.
IF BIT 6 is `1'
The first effect that writing a new value to bits [5:0] will have is that PLL3 will go out of lock, and the Clock
control circuit will immediately inhibit FCLK and BCLK, without first verifying that SDRAM operations have
completed.
5.3.5 PMU Debounce Counter Test Register (PMUDBCT)
Bits Type
31:9 -
8
W
7:6 -
5
R
4
R/W
3
R/W
2:0 R/W
0x80001030
Function
Read
Write
Reserved
Reset: Normal operation
Set: Forces FCLK and BLCK to be active in all PMU states (test purposes only)
Reserved
Selected debounce counter bits
Reserved
Reset: normal operation
Set: disables Bus Request from the PMU to
allow CPU to read state machine for test
purposes during PMU IDLE state.
Prescaler bits
Reset: nTEST takes value from input pin
Set: forces local test mode
Select Debounce counter for
Value Function
0x0 nPMWAKEUP
0x1 RING event
0x3 Power Adapter event
0x4 Warm Reset
In order that the debounce counters (which would normally be clocked at 4 kHz) may be independently
exercised and observed, the counters may be triggered and observed using the above registers. These
registers are for testing only and are not required in normal use.
5.3.6 PMU PLL Test Register (PMUPLLTR)
31
…
Reserved
15
PMUTEST
7
14
PWRDN1
6
21
20
Select
LCLK,
CCLK
13
12
PWRDN2 PWRDN3
5
4
PLL3 Frequency
19
18
17
Select
BCLK
Select PLL Test
01(PLL1), 10(PLL2),
11(PLL3)
11
10
9
PLL1 Frequency
3
2
1
0x80001038
16
PLL TEST
MUX
8
0
Bits
31:21
20
19
Type
-
Function
Reserved
© 2004 MagnaChip Semiconductor Ltd. All Ri3g3hts Reserved.
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Version 1.1
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