HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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производитель

HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

4

R/w

OnEvt (debounced)

When reads, 0 = No On key event since last cleared; 1 = On key event since last cleared

When writes, OnEvt Interrupt Clear. Writing a `1' to this bit clears a pending interrupt bit.

3

R/w

PLLLock3

When reads,

0 = System PLL has been locked since last cleared

1 = System PLL has fallen out of lock since last cleared

When writes, writing a `1' to this bit causes the PLL3 Unlock event flag to be cleared.

2

R/w

PLLLock2

When reads,

0 = Comms PLL has been locked since last cleared

1 = Comms PLL has fallen out of lock since last cleared

When writes, writing a `1' to this bit causes the PLL2 Unlock event flag to be cleared.

1

R/w

PLLLock1

When reads,

0= LCD PLL has been locked since last cleared

1= LCD PLL has fallen out of lock since last cleared

When writes, writing a `1' to this bit causes the PLL1 Unlock event flag to be cleared.

0

R/w

PORStatus

When reads, 0 = No POR since last cleared; 1 = POR since last cleared

When writes, writing a `1' to this bit causes the nPOR event flag to be cleared.

5.3.4 PMU Clock Control Register (PMUCLK)

This register is used to control the frequency of PLL3, the system clock PLL and PLL1, the LCD clock. Six bits

are defined which control the frequency of FCLK, and a further bit is used to control the frequency of PLL1, the

LCD clock. The Default (Power on Reset) value for this register is 0x2126.

0x80001028

15

14

13

12

11

10

9

8

PLL2

ENABLE

PLL1

ENABLE

PLL1 FREQ

7

6

5

4

3

2

1

0

PLL3

MUTE

PLL3

FREQ

UPDATE

PLL3 FREQ

Bits

31:16

15

Type

-

R/W

14 R/W

13:8 R/W

7

R/W

6

R/W

5:0 R/W

Function

Reserved

Set for PLL2 enable. Output will be gated until PLL2 Lock Detect (LD) is received. Reset for

disable PLL2

Set for PLL1 enable. Output will be gated until PLL1 Lock Detect (LD) is received. Reset for

disable PLL1

Same with bit [5:0]. But output clock frequency will be half of PLL3 – default 30.4128 MHz

Reset: PLL3 is muted when Lock detect = 0 (default)

Set: PLL3 only muted after nPOR or nRESET. Subsequent unlock condition does not mute

the clock. Allows dynamic changes to the clock frequency without halting execution. Care: this

only will be legal if PLL3 is under-damped (i.e. will not exhibit overshoot in its lock behavior).

Reset: PLL3 frequency control frequency is only updated when PMU exits DEEP SLEEP

mode (default)

Set: PLL3 frequency control frequency is updated instantaneously

Value Frequency Value Frequency

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

49.7664 MHz

51.6096 MHz

53.4528 MHz

55.2960 MHz

57.1392 MHz

58.9824 MHz

60.8256 MHz

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

68.1984 MHz

70.0416 MHz - default

71.8848 MHz

73.7280 MHz

75.5712 MHz

77.4144 MHz

79.2576 MHz

© 2004 MagnaChip Semiconductor Ltd. All Ri3g2hts Reserved.

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Version 1.1

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