HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

One other possible application is to use the nDCD signal, from the UART interface, as a wake up source, by

connecting nDCD to a PORTB input. In Deep Sleep mode, nDCD can wake up the system by generating a

PORTB interrupt request to the PMU block. The PMU state machine then returns the system to the

operational mode.

5.3 Registers

Address

Name

Width

0x8000.1000 PMUMODE 4

0x8000.1010 PMUID

32

0x8000.1020 PMUSTAT 17

0x8000.1028 PMUCLK

16

0x8000.1030 PMUDBCT 9

0x8000.1038 PUMPLLTR 21

Table 5-1 PMU Register Summary

Default

0x1B

Description

PMU Mode Register

PMU ID Register

PMU Reset/PLL Status Register

PMU Clock Control Register

PMU Debounce Test Register

PMU PLL Test Register

5.3.1 PMU Mode Register (PMUMODE)

This read/write register is to change from RUN mode or SLOW mode into a different mode. The encoding is shown below, in

PMU Mode encoding. The register can only be accessed in RUN mode or SLOW mode (these are the only modes in which

the processor is active). Therefore, the processor will never be able to read values for modes other than mode 0x00 and

mode 0x 01. A test controller may read other values as long as clocks are enabled with bit 8 of the PMU Debounce Counter

Test Register. For more information, please refer 5.3.6.

0x80001000

31

…

3

2

1

0

WAKEUP MODE SEL

Bits Type

31:4 -

3

R/W

2:0 R/W

Function

Reserved

Writing a `1' to this bit allows PMU to exit DEEP SLEEP mode when pins PMBATOK and

PMADAPOK are both low. Writing a `0' to this bit prevents the PMU from leaving DEEP

SLEEP mode when PMBATOK and PMADAPOK are both low

Value PMU Mode encoding

0x04 Initialization mode

0x01 RUN mode

0x00 SLOW mode

0x02 IDLE mode

0x03 SLEEP mode

0x07 DEEP SLEEP mode

Note: All other values in the above table are undefined.

5.3.2 PMU ID Register (PMUID)

This read-only register returns a unique chip revision ID. Revision 0 of the HMS30C7202 device (the first

revision) will return the constant value 0x00720200.

0x80001010

31

…

0

0x00720200

5.3.3 PMU Reset /PLL Status Register (PMUSTAT)

This read/write register provides status information on power on reset and the PLL status. The allocation is a

shown in following two tables: ResetStatus Register Bits. The bits in this register are `sticky' bits. For a

definition of a sticky bit, please refer to 5.2.3 Wake-up Debounce and Interrupt. Generally, this register will be

© 2004 MagnaChip Semiconductor Ltd. All Ri3g0hts Reserved.

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