HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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производитель

HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

Pin Name

TCLK

nTRST

TMS

TDI

Internal Resistor

Pullup

Pulldown

Pullup

Pullup

11.3.3 Instruction Register

The instruction register is 4 bits in length.

There is no parity bit. The fixed value loaded into the instruction register during the CAPTURE-IR controller

state is: 0001.

11.3.4 Public Instructions

The following public instructions are supported:

Instruction

EXTEST

SAMPLE/PRELOAD

CLAMP

HIGHZ

CLAMPZ

INTEST

IDCODE

BYPASS

Binary Code

0000

0011

0101

0111

1001

1100

1110

1111

In the descriptions that follow, TDI and TMS are sampled on the rising edge of TCK and all output transitions

on TDO occur as a result of the falling edge of TCK.

EXTEST (0000)

The BS (boundary-scan) register is placed in test mode by the EXTEST instruction.The EXTEST instruction

connects the BS register between TDI and TDO.When the instruction register is loaded with the EXTEST

instruction, all the boundary-scan cells are placed in their test mode of operation.

In the CAPTURE-DR state, inputs from the system pins and outputs from the boundary-scan output cells to

the system pins are captured by the boundary-scan cells. In the SHIFT-DR state, the previously captured test

data is shifted out of the BS register via the TDO pin, whilst new test data is shifted in via the TDI pin to the BS

register parallel input latch. In the UPDATE-DR state, the new test data is transferred into the BS register

parallel output latch. Note that this data is applied immediately to the system logic and system pins. The first

EXTEST vector should be clocked into the boundary-scan register, using the SAMPLE/PRELOAD instruction,

prior to selecting EXTEST to ensure that known data is applied to the system logic.

SAMPLE/PRELOAD (0011)

The BS (boundary-scan) register is placed in normal (system) mode by the SAMPLE/PRELOAD instruction.

The SAMPLE/PRELOAD instruction connects the BS register between TDI and TDO.

When the instruction register is loaded with the SAMPLE/PRELOAD instruction, all the boundary-scan cells

are placed in their normal system mode of operation.

In the CAPTURE-DR state, a snapshot of the signals at the boundary-scan cells is taken on the rising edge of

TCK. Normal system operation is unaffected. In the SHIFT-DR state, the sampled test data is shifted out of

the BS register via the TDO pin, whilst new data is shifted in via the TDI pin to preload the BS register parallel

input latch. In the UPDATE-DR state, the preloaded data is transferred into the BS register parallel output

latch. Note that this data is not applied to the system logic or system pins while the SAMPLE/PRELOAD

© 2004 MagnaChip Semiconductor Ltd. All R1ig49hts Reserved.

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