HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

00

P_D

78

TCNT

FD

FE

FF

00

01

10

11

12

13

14

RSTCSR

00011111

10011111

00011111

TCSR

01111000

01111000

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

Figure 10-10 Interrupt Clear in the watchdog timer mode with reset disable

10.9.3.3Watchdog Timer Mode with Manual Reset

TCNT = 0x00 TRCR = 0xF8

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

P_D

TCNT

FD

FE

FF

00

01

10

11

12

13

14

RSTCSR

01111111

11111111

01111111

TCSR

01111000

01111000

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

Figure 10-11 Interrupt Clear in the watchdog timer mode with manual reset

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