HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor
Номер в каталоге
Компоненты Описание
производитель
HMS30C7202N Datasheet PDF : 179 Pages
| |||
HMS30C7202N
001
Third
Transmitter Holding Register Empty
Transmitter Holding Register Empty
Reading the IIR Register (if source of interrupt) or writing into the Transmitter Holding
Register
000
Fourth
MODEM Status
Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect
Reading the MODEM Status Register
0
R
This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is
pending. When bit 0 is logic 0, an interrupt is pending and the IIR contents may be used as a
pointer to the appropriate interrupt service routine. When bit 0 is logic 1, no interrupt is
pending
FIFO Control Register
This is a write-only register at the same location as the IIR (the IIR is a read-only register). This register is
used to enable the FIFOs, clear the FIFOs and set the RCVR FIFO trigger level.
Bits Type
7:6 W
5:3 -
2
W
1
W
0
W
Function
These two bits sets the trigger level for the RCVR FIFO interrupt
Value RCVR FIFO Trigger Level (Bytes)
00
01
01
04
10
08
11
14
Reserved
Writing 1 resets the transmitter FIFO counter logic to 0. The shift register is not cleared. The 1
that is written to this bit position is self-clearing
Writing 1 resets the receiver FIFO counter logic to 0. The shift register is not cleared. The 1
that is written to this bit position is self-clearing
Writing 1 enables both the XMIT and RCVR FIFOs. Resetting FCR0 will clear all bytes in both
FIFOs. When changing from FIFO Mode to 16C450 Mode and vice versa, data is
automatically cleared from the FIFOs. This bit must be a 1 when other FCR bits are written to
or they will not be programmed
10.8.2.4 LCR
The system programmer specifies the format of the asynchronous data communications exchange and set the
Divisor Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of
the Line Control Register. The read capability simplifies system programming and eliminates the need for
separate storage in system memory of the line characteristics.
UxBase+0x0C
7
6
5
4
3
2
1
0
DLAB
SET
BREAK
STICK
PARITY
EVEN
PARITY
PARITY
ENABLE
STOPBIT
NUMBER
WORD
SELECT
LENGTH
Bits Type
7
6
Function
This bit is the Divisor Latch Access Bit (DLAB). It must be set HIGH (logic 1) to access the
Divisor Latches of the Baud Generator during a Read or Write operation. It must be set LOW
(logic 0) to access the Receiver Buffer, the Transmitter Holding Register or the Interrupt
Enable Register
This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving
© 2004 MagnaChip Semiconductor Ltd. All R1ig36hts Reserved.
- 136 -
Version 1.1
Share Link: 