HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

11 DEBUG AND TEST INTERFACE

11.1 Overview

The HMS30C7202 has built-in features that enable debug and test in a number of different contexts. Firstly,

there are circuit structures to help with software development. Secondly, the device contains boundary scan

cells for circuit board test. Finally, the device contains some special test modes that enable the generation

production patterns for the device itself.

11.2 Software Development Debug and Test Interface

The ARM720T and Piccolo processors incorporated inside HMS30C7202 contain hardware extensions for

advanced debugging features. These are intended to ease user development and debugging of application

software, operating systems, and the hardware itself.

Full details of the debug interfaces and their programming can be found in ARM720T Data Sheet (ARM DDI-

0087) and Piccolo Data Sheet (ARM DDI-0128). The MultiICE product enables the ARM720T and Piccolo

macrocells to be debugged in one environment. Refer to Guide to MultiICE (ARM DUI-0048).

11.3 Test Access Port and Boundary-Scan

HMS30C7202 contains full boundary scan on its inputs and outputs to help with circuit board test. This

supports both INTEST and EXTEST, allowing patterns to be applied serially to the HMS30C7202 when fixed

in a board and for full circuit board connection respectively. The boundary-scan interface conforms to the IEEE

Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture. (Please refer to this standard

for an explanation of the terms used in this section and for a description of the TAP controller states.) The

boundary-scan interface provides a means of testing the core of the device when it is fitted to a circuit board,

and a means of driving and sampling all the external pins of the device irrespective of the core state. This

latter function permits testing of both the device's electrical connections to the circuit board, and (in

conjunction with other devices on the circuit board having a similar interface) testing the integrity of the circuit

board connections between devices. The interface intercepts all external connections within the device, and

each such “cell” is then connected together to form a serial register (the boundary scan register). The whole

interface is controlled via 5 dedicated pins: TDI, TMS, TCK, nTRST and TDO. Figure 11-1: Test Access Port

(TAP) Controller State Transitions shows the state transitions that occur in the TAP controller.

© 2004 MagnaChip Semiconductor Ltd. All R1ig47hts Reserved.

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