CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1318BV18
(Rev.:2004)

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

TAP AC Switching Characteristics Over the Operating Range[26, 27] (continued)

Parameter

Description

Set-up Times

tTMSS

TMS Set-up to TCK Clock Rise

tTDIS

TDI Set-up to TCK Clock Rise

tCS

Capture Set-up to TCK Rise

Hold Times

tTMSH

TMS Hold after TCK Clock Rise

tTDIH

TDI Hold after Clock Rise

tCH

Capture Hold after Clock Rise

Output Times

tTDOV

tTDOX

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TAP Timing and Test Conditions[27]

0.9V

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

Min.

Max.

Unit

10

ns

10

ns

10

ns

10

ns

10

ns

10

ns

20

ns

0

ns

TDO

Z0 = 50Ω

50Ω

CL = 20 pF

(a) GND

0V

tTH

tTL

ALL INPUT PULSES

1.8V

0.9V

Test Clock

TCK

Test Mode Select

TMS

Test Data-In

TDI

tTMSS

tTDIS

tTCYC

tTMSH

tTDIH

Test Data-Out

TDO

tTDOV

tTDOX

Document Number: 38-05621 Rev. **

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