CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1318BV18
(Rev.:2004)

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

Capacitance[15]

CIN

CCLK

CO

Parameter

PRELIMINARY

Description

Input Capacitance

Clock Input Capacitance

Output Capacitance

Test Conditions

TA = 25°C, f = 1 MHz,

VDD = 1.8V

VDDQ = 1.5V

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

Max.

Unit

TBD

pF

TBD

pF

TBD

pF

AC Test Loads and Waveforms

VREF

OUTPUT

Device

Under

Test

ZQ

(a)

0.75V

Z0 = 50Ω

RQ =

250Ω

VREF

RL = 50Ω

VREF = 0.75V

OUTPUT

Device

Under ZQ

Test

INCLUDING

JIG AND

SCOPE

VREF = 0.75V

0.75V

R = 50Ω

RQ =

250Ω

(b)

5 pF 0.25V

[14]

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2V/ns

Document Number: 38-05621 Rev. **

Page 13 of 24

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