CY7C1318BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1318BV18
(Rev.:2004)

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

TAP Controller Block Diagram

PRELIMINARY

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

Selection

Circuitry

TDI

0

Bypass Register

210

Instruction Register

Selection

Circuitry

TDO

31 30 29 . . 2 1 0

Identification Register

106 . . . . 2 1 0

Boundary Scan Register

TCK

TAP Controller

TMS

TAP Electrical Characteristics Over the Operating Range[9, 11, 25]

Parameter

VOH1

VOH2

VOL1

VOL2

VIH

VIL

IX

Description

Output HIGH Voltage

Output HIGH Voltage

Output LOW Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input and OutputLoad Current

Test Conditions

IOH = −2.0 mA

IOH = −100 µA

IOL = 2.0 mA

IOL = 100 µA

GND ≤ VI ≤ VDD

Min.

1.4

1.6

0.65VDD

–0.3

−5

Max.

Unit

V

V

0.4

V

0.2

V

VDD + 0.3

V

0.35VDD

V

5

µA

TAP AC Switching Characteristics Over the Operating Range[26, 27]

Parameter

Description

Min.

Max.

tTCYC

TCK Clock Cycle Time

50

tTF

TCK Clock Frequency

20

tTH

TCK Clock HIGH

40

tTL

TCK Clock LOW

40

Notes:

25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

26. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

27. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Unit

ns

MHz

ns

ns

Document Number: 38-05621 Rev. **

Page 19 of 24

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