CY7C1316BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1316BV18
(Rev.:2004)

18-Mbit DDR-II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

Write Cycle Descriptions[2, 8] (CY7C1320BV18) (continued)

BWS0 BWS1 BWS2 BWS3 K

H

H

H

L

–

H

H

H

H

L-H

H

H

H

H

–

K

Comments

L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is

written into the device. D[26:0] will remain unaltered.

– No data is written into the device during this portion of a Write operation.

L-H No data is written into the device during this portion of a Write operation.

Write Cycle Descriptions[2, 8](CY7C1916BV18)

BWS0

L

L

H

H

K

K Comments

L-H

– During the Data portion of a Write sequence,

the single byte (D[8:0]) is written into the device.

–

L-H During the Data portion of a Write sequence,

the single byte (D[8:0]) is written into the device.

L-H

– No data is written into the device during this portion of a Write operation.

–

L-H No data is written into the device during this portion of a Write operation.

Document Number: 38-05621 Rev. **

Page 11 of 24

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