CY7C1316BV18(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1316BV18 Datasheet PDF : 24 Pages
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PRELIMINARY
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Switching Characteristics Over the Operating Range [16,17]
Cypress Consortium
Parameter Parameter
Description
tPOWER
VDD(Typical) to the first Access[18]
tCYC
tKHKH
K Clock and C Clock Cycle Time
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
tKL
tKLKH
Input Clock (K/K and C/C) LOW
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising
edge to rising edge)
250 MHz 200 MHz
Min. Max. Min. Max.
1
1
4.0 6.3 5.0 7.9
1.6 – 2.0 –
1.6 – 2.0 –
1.8 – 2.2 –
167 MHz
Min. Max.
1
6.0 8.4
2.4 –
2.4 –
2.7 –
tKHCH
tKHCH
Set-up Times
K/KClockRisetoC/CClockRise(risingedgetorisingedge) 0.0 1.8 0.0 2.2 0.0 2.7
tSA
tSA
tSC
tSC
tSCDDR
tSC
tSD
tSD
Hold Times
Address Set-up to K Clock Rise
0.5 – 0.6 – 0.7 –
Control Set-up to Clock (K, K) Rise (LD, R/W)
0.5 – 0.6 – 0.7 –
Double Data Rate Control Set-up to Clock (K, K) 0.35 – 0.4 – 0.5 –
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Set-up to Clock (K and K) Rise
0.35 – 0.4 – 0.5 –
tHA
tHA
tHC
tHC
tHCDDR
tHC
tHD
tHD
Output Times
Address Hold after Clock (K and K) Rise
0.5 – 0.6 – 0.7 –
Control Hold after Clock (K and K) Rise (LD, R/W) 0.5 – 0.6 – 0.7 –
Double Data Rate Control Hold after Clock (K and 0.35 – 0.4 – 0.5 –
K) Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Hold after Clock (K and K) Rise
0.35 – 0.4 – 0.5 –
tCO
tDOH
tCHQV
tCHQX
C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.50
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45 – –0.45 – –0.50 –
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
– 0.45 – 0.45 – 0.50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCQOH
tCHCQX
tCQD
tCQHQV
tCQDOH
tCQHQX
tCHZ
tCHZ
tCLZ
tCLZ
DLL Timing
Echo Clock Hold after C/C Clock Rise
–0.45 – –0.45 – –0.50 – ns
Echo Clock High to Data Valid
– 0.30 – 0.35 – 0.40 ns
Echo Clock High to Data Invalid
–0.30 – –0.35 – –0.40 – ns
Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20] – 0.45 – 0.45 – 0.50 ns
Clock (C and C) Rise to Low-Z[19, 20]
–0.45 – –0.45 – –0.50 – ns
tKC Var
tKC Var
Clock Phase Jitter
– 0.20 – 0.20 – 0.20 ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024 – 1024 – 1024 – Cycles
tKC Reset tKC Reset
K Static to DLL Reset
30
30
30
ns
Shaded areas contain advance information.
Notes:
15. Tested initially and after any design or process change that may affect these parameters.
16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 38-05621 Rev. **
Page 14 of 24
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