HMP8156 Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

HMP8156

NTSC/PAL Encoder

Intersil 

HMP8156

BIT

NUMBER

FUNCTION

7-0

Assert BLANK

Output Signal

(Vertical)

TABLE 25. START V_BLANK LOW REGISTER

SUB ADDRESS = 23H

DESCRIPTION

This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit

start_vertical_blank register. During normal operation, it specifies the line number (n) to

start ignoring pixel input data (and what line number to start blanking the output video)

each odd field; for even fields, it occurs on line (n + 262) or (n + 313).

During SIF input mode, the register value (n) specifies the line number to start ignoring

pixel input data each noninterlaced input frame. The output video will be blanked starting

on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).

The leading edge of VSYNC at the start of an odd field is count 000H (note that this does

not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK

is configured as an output.

RESET

STATE

03H

BIT

NUMBER

FUNCTION

7-1

Reserved

0

Assert BLANK

Output Signal

(Vertical)

TABLE 26. START V_BLANK HIGH REGISTER

SUB ADDRESS = 24H

DESCRIPTION

RESET

STATE

0000000B

This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit

1B

start_vertical_blank register. This register is ignored unless BLANK is configured as an

output.

BIT

NUMBER

FUNCTION

7-0

Negate BLANK

Output Signal

(Vertical)

TABLE 27. END V_BLANK REGISTER

SUB ADDRESS = 25H

DESCRIPTION

During normal operation, this 8-bit register specifies the line number (n) to start inputting

pixel input data (and what line number to start generating active output video) each odd

field; for even fields, it occurs on line (n + 262) or (n + 313).

During SIF input mode, the register value (n) specifies the line number to start inputting

pixel input data each noninterlaced input frame. The output video will be active starting

on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).

The leading edge of VSYNC at the start of an odd field is count 000H (note that this does

not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK

is configured as an output.

RESET

STATE

13H

21

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