MFC2000 Просмотр технического описания (PDF) - Conexant Systems

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Компоненты Описание

производитель

MFC2000

Multifunctional Peripheral Controller 2000

Conexant Systems 

Tables

Table 1-1. Reference Documentation.................................................................................................................................... 1-5

Table 2-1. MFC2000 Device Family ...................................................................................................................................... 2-1

Table 3-1. Pin Description (1 of 6) ......................................................................................................................................... 3-1

Table 3-2. Maximum Ratings................................................................................................................................................. 3-7

Table 3-3. Digital Input Characteristics .................................................................................................................................. 3-8

Table 3-4. Output Characteristics .......................................................................................................................................... 3-8

Table 3-5. Power Supply Requirements ................................................................................................................................ 3-9

Table 3-6. Battery Power Supply Current Requirements....................................................................................................... 3-9

Table 4-1. Fixed-Location and Size Chip Selects .................................................................................................................. 4-4

Table 4-2. Operation Register Map (1 of 9) ........................................................................................................................... 4-8

Table 4-3. Setup Registers (1 of 2)...................................................................................................................................... 4-17

Table 4-4. Cache Tag Data Format (for Test Mode Read/Write Operation) ........................................................................ 4-20

Table 4-5. Access Modes for Reading ROM ....................................................................................................................... 4-27

Table 4-6. Read Operation (Internal Peripheral Gets Data From Memory) ......................................................................... 4-29

Table 4-7. Write Operation (Internal Peripheral Puts Data Into Memory) ............................................................................ 4-29

Table 4-8. Read/Write with Wait States Timing Parameters................................................................................................ 4-45

Table 4-9. MFC2000 Interrupt and Reset Signals ............................................................................................................... 4-46

Table 4-10. Programmable Resolution of Timer1 and Timer2 ............................................................................................. 4-53

Table 4-11. DRAM Wait State Configurations ..................................................................................................................... 4-55

Table 4-12. Address MultiplexingPart 1 ........................................................................................................................... 4-57

Table 4-13. Address MultiplexingPart 2 ........................................................................................................................... 4-57

Table 4-14. DRAM Row/Column Configuration ................................................................................................................... 4-58

Table 4-15. DRAM Timing Parameters................................................................................................................................ 4-71

Table 4-16. Feature Matrix .................................................................................................................................................. 4-77

Table 4-17. DMA Channel Functions and Characteristics ................................................................................................... 4-78

Table 4-18 DMA Channel 3 Control Bit Sssignment............................................................................................................ 4-79

Table 6-1. Operation Mode Frequencies ............................................................................................................................... 6-1

Table 7-1. Register setup for Rohm–IA3008–ZE22............................................................................................................. 7-27

Table 7-2. Register setup for Dyna–DL507–07UAH............................................................................................................ 7-29

Table 7-3. Register setup for Mitsubishi-GT3R216.............................................................................................................. 7-31

Table 7-4. Register Setup for Toshiba–CIPS218MC300 ..................................................................................................... 7-33

Table 7-5. Register Setup for NEC – µPD3724 ................................................................................................................... 7-35

Table 7-6. Register setup for NEC – µPD3794.................................................................................................................... 7-37

Table 7-7. Register Setup for SONY – ILX516K.................................................................................................................. 7-39

Table 8-1. Untitled Table ....................................................................................................................................................... 8-2

Table 8-2. Untitled Table ....................................................................................................................................................... 8-2

Table 8-3. Offset Adjustment on DAC ................................................................................................................................... 8-2

Table 8-4. Programmable Gain Amplifier (PGA).................................................................................................................... 8-3

Table 8-5. Pipelined ADC (PADC)......................................................................................................................................... 8-4

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