MFC2000 Просмотр технического описания (PDF) - Conexant Systems

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MFC2000

Multifunctional Peripheral Controller 2000

Conexant Systems 

Figure 7-31. DMA Operation................................................................................................................................................ 7-55

Figure 8-1. Untitled Figure ..................................................................................................................................................... 8-1

Figure 9-1: Bi-level Resolution Conversion Block Diagram ................................................................................................... 9-2

Figure 9-2. The Physical Nozzle Diagram for Typical Inkjet Heads ....................................................................................... 9-5

Figure 9-3. Untitled Figure ..................................................................................................................................................... 9-5

Figure 9-4: Resolution Conversion Programming................................................................................................................ 9-15

Figure 10-1. Print ASIC Interface......................................................................................................................................... 10-2

Figure 11-1. Nozzle Diagram of a Typical Programmable Inkjet Head ................................................................................ 11-1

Figure 11-2. Examples of Nozzle Head Configurations ....................................................................................................... 11-2

Figure 11-3. Nozzle Configuration by Bit Rotation Block (Regardless of Physical Nozzle Configuration) ........................... 11-2

Figure 11-4. MFC2000 Bit Rotation Block Diagram............................................................................................................. 11-3

Figure 11-5. Fetcher DMA Channel Fetch Order................................................................................................................. 11-4

Figure 11-6. CPU Background Print Data Preparation ...................................................................................................... 11-12

Figure 11-7. MFC2000 Little-Endian Format ..................................................................................................................... 11-13

Figure 12-1. Vertical Printer Motor Control Block Diagram .................................................................................................. 12-1

Figure 12-2. Stepping Timing .............................................................................................................................................. 12-2

Figure 12-3. Scan Motor Control Diagram ........................................................................................................................... 12-5

Figure 12-4. Stepping Timing .............................................................................................................................................. 12-7

Figure 12-5: Current Control Diagram ................................................................................................................................. 12-9

Figure 14-1. Data Flow for Compression/Decompression ................................................................................................... 14-1

Figure 14-2. Compressor/Decompressor FIFO Structure .................................................................................................... 14-2

Figure 15-1. SASIF Block Diagram...................................................................................................................................... 15-2

Figure 15-2. SASSCLK Timing Diagram............................................................................................................................ 15-12

Figure 15-3. Synchronous Mode Timing............................................................................................................................ 15-13

Figure 15-4. Asynchronous Transmitter Timing................................................................................................................. 15-14

Figure 17-1. Parallel Port Interface Controller Block Diagram ............................................................................................. 17-3

Figure 17-2. Compatibility Mode Timing Diagram.............................................................................................................. 17-16

Figure 17-3. Nibble Mode Data Transfer Cycle ................................................................................................................. 17-17

Figure 17-4. BYTE Mode Data Transfer Cycle .................................................................................................................. 17-18

Figure 17-5. ECP Mode Timing Diagram........................................................................................................................... 17-19

Figure 17-6. Reverse ECP Transfer Timing....................................................................................................................... 17-20

Figure 17-7. Error Cycle Timing Diagram .......................................................................................................................... 17-21

Figure 18-1. RTC Block Diagram......................................................................................................................................... 18-1

Figure 19-1. SSIF Block Diagram ........................................................................................................................................ 19-1

Figure 19-2. SSCLK1 Diagram ............................................................................................................................................ 19-3

Figure 19-3. SSCLK2 Diagram ............................................................................................................................................ 19-6

Figure 19-4. Timing Diagram ............................................................................................................................................... 19-8

Figure 20-1. Bell/Ringer Timing ........................................................................................................................................... 20-1

Figure 20-2. Bell/Ringer Block Diagram .............................................................................................................................. 20-2

Figure 20-3. Bell/Ringer Generator Waveform .................................................................................................................... 20-3

Figure 20-4. Tone Generator Frequency Change................................................................................................................ 20-6

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